參數(shù)資料
型號(hào)： SX8725E083TRT
元件分類： ADC
英文描述： 3-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO12
封裝： 4 X 4 MM, ROHS COMPLIANT, MLPD-12
文件頁(yè)數(shù)： 51/53頁(yè)
文件大小： 3966K
代理商： SX8725E083TRT
ADVANCED COMMUNICATIONS & SENSING
V1.8 2009 Semtech Corp.
www.semtech.com
7
SX8725
ZoomingADC for Pressure and Temperature Sensing
Parameter
Symbol
Comments / Conditions
Min
Typ
Max
Unit
Nbr of End Conversion Cycles
NEND
0
5
cycles
PGA Stabilization Delay
(Note 15)
OSR
cycles
ADC Digital Output
Output Data Coding
Binary Two’s Complement
See Table 15 and Table 16
Power Supply
Voltage Supply Range
VDD
2.4
5
5.5
V
Analog Quiescent Current
Only ZoomingADC
Total Consumption
IQ
VDD = 5V/3V
800/675
A
ADC Only Consumption
VDD = 5V/3V
260/190
A
PGA1 Consumption
VDD = 5V/3V
190/170
A
PGA2 Consumption
VDD = 5V/3V
150/135
A
PGA3 Consumption
VDD = 5V/3V
200/180
A
Analog Power Dissipation
All PGAs & ADC Active
Normal Power Mode
VDD = 5V/3V (Note 16)
4.0/2.0
mW
3/4 Power Reduction Mode
VDD = 5V/3V (Note 17)
3.2/1.6
mW
1/2 Power Reduction Mode
VDD = 5V/3V (Note 18)
2.4/1.1
mW
1/4 Power Reduction Mode
VDD = 5V/3V (Note 19)
1.5/0.7
mW
Temperature
Operating Range
-40
125
°C
Notes:
(1)
Gain
defined
as
overall
PGA
gain
GDTOT
=
GD1
GD
2
GD
3.
Maximum
input
voltage
is
given
by:
VIN, MAX =
±(V
REF,ADC/2)
(OSR/OSR+1).
(2)
Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1.
(3)
Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is fS =
500kHz. This figure must be multiplied by 2 for fS = 250kHz, 4 for fS = 125kHz. Input impedance is proportional to 1/ fS.
(4)
Figure independent on PGA1 gain and sampling frequency fS.
(5)
Figure independent on PGA2 gain and sampling frequency fS.
(6)
Figure independent on PGA3 gain and sampling frequency fS.
(7)
Resolution is given by n = 2
log2(OSR) + log2(N
ELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1,
2, 4 or 8.
(8)
If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data.
(9)
Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function
(with the offset error removed).
(10) Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For
± 1 LSB offset, N
ELCONV must be
≥2.
(11) INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds
over the full scale. (For 16 bits INL set PGA3 on).
(12) DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes.
(13) Figures for Gains = 1 to 100. PSRR is defined as the amount of change in the ADC output value as the power supply voltage
changes.
(14) Conversion time is given by: TCONV = (NELCONV
(OSR + 1) + 1) / f
S. OSR can be set between 8 and 1024, in powers of 2. NELCONV can
be set to 1, 2, 4 or 8.
(15) PGAs are reset after each writing operation to registers RegACCfg1-5. The ADC must be started after a PGA or inputs common-
mode stabilization delay. This is done by writing bit Start several cycles after PGA settings modification or channel switching. Delay
between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of cycles.
This delay does not apply to conversions made without the PGAs.
(16) Nominal (maximum) bias currents in PGAs and ADC, i.e. IB_AMP_PGA[1:0] = '11' and IB_AMP_ADC[1:0] = '11'.
(17) Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = '10', IB_AMP_ADC[1:0] = '10'.
(18) Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = '01', IB_AMP_ADC[1:0] = '01'.
(19) Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = '00', IB_AMP_ADC[1:0] = '00'.
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