參數(shù)資料
型號(hào)： SX8724E082TDT
廠商： Semtech
文件頁(yè)數(shù)： 6/53頁(yè)
文件大?。?/td> 0K
描述： IC DAS PRESS/TEMP SENS 16MLPQ
標(biāo)準(zhǔn)包裝： 1
系列： ZoomingADC™
類(lèi)型： 數(shù)據(jù)采集系統(tǒng)（DAS）
輸入類(lèi)型： 差分
輸出類(lèi)型： 數(shù)字
接口： I²C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 16-MLPQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 585 (CN2011-ZH PDF)
其它名稱(chēng)： SX8724E082TDTDKR
ADVANCED COMMUNICATIONS & SENSING
V1.23 2009 Semtech Corp.
www.semtech.com
14
SX8724
ZoomingADC for Pressure and Temperature Sensing
2-WIRE
The 2-WIRE interface gives access to the chip registers. It complies with the 2-WIRE protocol specifications,
restricted to the slave side of the communication.
General features:
Slave only operation
Fast mode operation (up to 400 kHz)
Combined read and write mode support
General call reset support
7-bit device address customization
Stretch 2-WIRE clock SCL only before sending ACK/NACK
The interface handles 2-WIRE communication at the transaction level: the processor is only aware of read and
writes transactions. A read transaction is an external request to get the content of system memory location and
a write transaction is an external request to write the content of a system memory location.
2-WIRE Communication Format
Figure 5 - Timing Diagram for Reading from SX8724
Figure 6 - Timing Diagram for Writing to the SX8724
Figure 7 - Timing Diagram for Reading an ADC Sample from SX8724
2-WIRE Address
The default 2-WIRE slave address is 1001000 in binary.
This is the standard part 2-WIRE slave address. Other addresses between 1001001 and 1001111 are available
by special request.
Start
Slave Address
ACK
W
Memory Address
ACK
Start
Slave Address
ACK
R
Data
NACK Stop
Master
SX8724
1
0
1
0
1
9
1
9
1
9
1
9
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
SDA
SCL
Start
Slave Address
ACK
W
Memory Address
ACK
Start
Slave Address
ACK
W
Data
ACK Stop
Master
SX8724
Master
SX8724
Master
SX8724
1
9
1
9
1
9
1
9
1
0
1
0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
SDA
SCL
Start
Slave Address
ACK
W
RegACOutMsb
ACK
Start
Slave Address
ACK
R
Data
NACK Stop
Master
SX8724
1
0
1
0
1
9
1
9
1
9
1
9
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
SDA
SCL
Ready
1
0
1
Start
Slave Address
ACK
W
RegACOutLsb
ACK
Start
Slave Address
ACK
R
Data
NACK Stop
Master
SX8724
1
0
1
0
1
9
1
9
1
9
1
9
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
SDA
SCL
Ready
1
0
...
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