參數(shù)資料
型號: SX8723E083TDT
廠商: Semtech
文件頁數(shù): 50/53頁
文件大?。?/td> 0K
描述: IC DAS PRESS/TEMP SENS 12MLPD
標準包裝: 1
系列: ZoomingADC™
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
輸入類型: 差分
輸出類型: 數(shù)字
接口: I²C
安裝類型: 表面貼裝
封裝/外殼: 12-BFDFN 裸露焊盤
供應商設備封裝: 12-MLPD
包裝: 標準包裝
產品目錄頁面: 585 (CN2011-ZH PDF)
其它名稱: SX8723E083TDTDKR
ADVANCED COMMUNICATIONS & SENSING
V1.8 2009 Semtech Corp.
www.semtech.com
6
SX8723
ZoomingADC for Pressure and Temperature Sensing
ZoomingADC Specifications
Unless otherwise specified: Temperature TA = +25° C, VDD = +5V, GND = 0V, VREF, ADC = +5V, VIN = 0V, over-sampling frequency
fS = 250 kHz, PGA3 on with Gain = 1, PGA1&PGA2 off, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IB_AMP_ADC[1:0] =
IB_AMP_PGA[1:0] = '01'). For resolution n = 12 bits: OSR = 32 and NELCONV = 4. For resolution n = 16 bits: OSR = 512 and NELCONV = 2.
Bandgap chopped at NELCONV rate.
Parameter
Symbol
Comments / Conditions
Min
Typ
Max
Unit
Analog Input
Gain = 1, OSR = 32 (Note 1)
-2.42
2.42
V
Gain = 100, OSR = 32
-24.2
24.2
mV
Differential Input Voltage Ranges
VIN = (VINP - VINN)
Gain = 1000, OSR = 32
-2.42
2.42
mV
Reference Voltage Range
VREF, ADC = (VREFP – VREFN)
VDD
V
Programmable Gain Amplifier (PGA)
Total PGA Gain
GDTOT
(Note 1)
1/12
1000
V/V
PGA1 Gain
GD1
See Table 5
1
10
V/V
PGA2 Gain
GD2
See Table 6
1
10
V/V
PGA3 Gain
GD3
Step = 1/12 V/V, See Table 8
0
127/12
V/V
Gain Setting Precision (each stage)
-3
±0.5
3
%
Gain Temperature Dependence
±5
ppm/°C
PGA2 Offset
GDoff2
Step = 0.2 V/V, See Table 7
-1
1
V/V
PGA3 Offset
GDoff3
Step = 1/12 V/V, See Table 9
-63/12
63/12
V/V
Offset Setting Precision (PGA2 or 3)
(Note 2)
-3
±0.5
3
%
Offset Temperature Dependence
±5
ppm/°C
Gain = 1 (Note 3)
1500
k
Input Impedance PGA1
Gain = 10 (Note 3)
150
k
Input Impedance PGA2, PGA3
Maximal gain (Note 3)
150
k
PGA1 (Note 4)
205
V
PGA2 (Note 5)
340
V
Output RMS noise
PGA3 (Note 6)
365
V
ADC Static Performance
Resolution, n
(Note 7)
6
16
Bits
No Missing Codes
(Note 8)
16
Bits
Gain Error
(Note 9)
±0.15
%
±1
%
Offset Error
n = 16 bits (Note 10)
±1
LSB
n = 12 Bits (Note 11)
±0.6
LSB
Integral Non-Linearity, INL
n = 16 Bits (Note 11)
±1.5
LSB
n = 12 Bits (Note 12)
±0.5
LSB
Differential Non-Linearity, DNL
n = 16 Bits (Note 12)
±0.5
LSB
Common Mode input range
VSS-0.3
VBATT+0.3
V
VDD = 5V
± 0.3V (Note 13)
78
dB
Power Supply Rejection Ratio
PSRR
VDD = 3V
± 0.3V (Note 13)
72
dB
ADC Dynamic Performance
n = 12 bits (Note 14)
133
cycles/fS
Conversion Time
TCONV
n = 16 bits (Note 14)
1027
cycles/fS
n = 12 bits, fS = 250kHz
1.88
kSps
Throughput Rate (Continuous Mode)
1/TCONV
n = 16 bits, fS = 250kHz
0.485
kSps
Nbr of Initialization Cycles
NINIT
0
2
cycles
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