參數(shù)資料
型號(hào)： SX8722I070TRLF
廠商： Semtech
文件頁(yè)數(shù)： 61/108頁(yè)
文件大?。?/td> 0K
描述： IC ZOOMING ADC 10BIT 16CH 44MLPQ
標(biāo)準(zhǔn)包裝： 1
類型： 壓力傳感器
輸入類型： 邏輯
輸出類型： 邏輯
接口： I²C
電流 - 電源： 300µA
安裝類型： 表面貼裝
封裝/外殼： 44-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 44-MLPQ（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 585 (CN2011-ZH PDF)
配用： XE8000EV120-ND - BOARD EVAL FOR SX8722I070TRLF
其它名稱： SX8722I070LFDKR
ACS - Revision 4.2
October 2008
2008 Semtech Corp.
www.semtech.com
Page 56
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
SX8722
High gain acquisition for sensor interface
12.5. ZoomingADC registers table
In table below the configuration of the peripheral registers is detailed. The system has a bank of eight 8-bit registers: six
registers are used to configure the acquisition chain (CxZAdcReg1 to 6), and two registers are used to store the output code
of the analog-to-digital conversion (CxDataOutMSB & LSB).
Table 40. ZoomingADC registers
Note Bits labelled R are reserved
With:
OUT:
(r) digital output code of the analog-to-digital converter. (MSB = OUT[15])
SET_NELC:
(rw) sets the number of elementary conversions to 2SET_NELC[1:0] . To compensate for offsets, the input signal is
chopped between elementary conversions (1,2,4,8).
SET_OSR:
(rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SET_OSR[2:0]) . OSR = 8, 16, 32, ..., 512,
1024.
CONT:
(rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit remains at 1.
IB_AMP_ADC:
(rw) sets the bias current in the ADC to 0.25 x (1+ IB_AMP_ADC[1:0]) of the normal operation current (25, 50, 75 or
100% of nominal current). To be used for low-power, low-speed operation.
IB_AMP_PGA:
(rw) sets the bias current in the PGAs to 0.25 x (1+ IB_AMP_PGA[1:0]) of the normal operation current (25, 50, 75 or
100% of nominal current). To be used for low-power, low-speed operation.
ENABLE:
(rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i = 1,2,3). PGA stages that
are disabled are bypassed.
FIN:
(rw) These bits set the sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency,
the sampling frequency is given as: 00 ' 1/4 fRC, 01 ' 1/8 fRC, 10 ' 1/32 fRC, 11' ~8kHz.
PGA1_GAIN:
(rw) sets the gain of the first stage: 0 ' 1, 1 ' 10.
PGA2_GAIN:
(rw) sets the gain of the second stage: 00 ' 1, 01 ' 2, 10 ' 5, 11 ' 10.
Register Name
Bit position
76543210
CxDataOutLSB
OUT[7:0]
CxDataOutMSB
OUT[15:8]
CxZadcReg1
Default values
R
0
SET_NC[1:0]
01
SET_OSR[2:0]
010
R
0
R
0
CxZadcReg2
Default value
IB_AMP_ADC[1:0]
11
IB_AMP_PGA[1:0]
11
ENABLE[3:0]
0001
CxZadcReg3
Default value
FIN[1:0]
00
PGA2_GAIN[1:0]
00
PGA2_OFFSET
0000
CxZadcReg4
Default value
PGA1_GAIN
0
PGA3_GAIN[6:0]
0000000
CxZadcReg5
Default value
0
PGA3_OFFSET[6:0]
0000000
CxZadcReg6
Default value
R
0
R
0
AMUX[4:0]
00000
VMUX
0
Not
Recommended
for
New
Designs
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