th July 2011 41 www.semtech.com SX8657/SX8658 Haptics " />
參數(shù)資料
型號(hào): SX8657IWLTRT
廠商: Semtech
文件頁(yè)數(shù): 36/61頁(yè)
文件大?。?/td> 0K
描述: IC TOUCH SCREEN 12BIT 20QFN
標(biāo)準(zhǔn)包裝: 1
類型: 電阻式,觸感驅(qū)動(dòng)器
觸摸面板接口: 4,5 線
輸入數(shù)/鍵: 1 TSC,雨刷,鑰匙
分辨率(位): 12 b
評(píng)估套件: *
數(shù)據(jù)接口: I²C,串行
電壓基準(zhǔn): 內(nèi)部
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-QFN(4x4)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: SX8657IWLDKR
ADVANCED COMMUNICATIONS & SENSING
Rev 1 – 25
th July 2011
41
www.semtech.com
SX8657/SX8658
Haptics Enabled 4/5-Wire
Resistive Touchscreen Controller with Proximity Sensing
10 RESET
10.1
Hardware (POR and NRST)
The chip generates its own power on reset (POR) signal after a power supply is connected to the VDD pin.
NRST input pin can be used to reset the chip anytime, it must be connected to VDD (or greater) either directly (if
not used), or via a resistor.
Figure 49 – Hardware Reset Conditions
1. Device behavior is undefined until VDD rises above VPOR, at which point internal reset procedure is
started and NIRQ is kept low.
2.
After tRESET, the reset procedure is completed and NIRQ is released high.
3.
In operation, the chip may be reset at anytime by an external device driving NRST low for tPULSE or
longer. NIRQ will go low during the reset phase and chip can be accessed normally again after NIRQ
rising edge. Additionally bit RESETSTAT will be set (cleared when reading RegStat)
10.2
Software (RegReset)
Writing 0xDE to RegReset register will reset the chip and all registers to their default values. NIRQ will go low
during the reset phase and chip can be accessed normally again after NIRQ rising edge. Additionally bit
RESETSTAT will be set (cleared when reading RegStat).
10.3
ESD Event (RESETSTAT)
In case of ESD event, the chip can reset to protect its internal circuitry. NIRQ will go low during the reset phase
and chip can be accessed normally again after NIRQ rising edge. Additionally bit RESETSTAT will be set
(cleared when reading RegStat).
Undefined
t
RESET
Reset
Signal
VDD
VPOR
t
PULSE
1
2
3
NIRQ
Undefined
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