th July 2011 43 www.semtech.com SX8654/SX8655/SX8656 H" />
參數(shù)資料
型號(hào)： SX8654IWLTRT
廠商： Semtech
文件頁(yè)數(shù)： 38/62頁(yè)
文件大?。?/td> 0K
描述： IC TOUCH SCREEN 12BIT 20QFN
標(biāo)準(zhǔn)包裝： 1
類型： 電阻式，觸感驅(qū)動(dòng)器
觸摸面板接口： 4，5 線
輸入數(shù)/鍵： 1 TSC，雨刷，鑰匙
分辨率（位）： 12 b
評(píng)估套件： *
數(shù)據(jù)接口： I²C，串行
電壓基準(zhǔn)： 內(nèi)部
電源電壓： 2.3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 20-QFN（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： SX8654IWLDKR
ADVANCED COMMUNICATIONS & SENSING
Rev 1 – 25
th July 2011
43
www.semtech.com
SX8654/SX8655/SX8656
Haptics Enabled 4/5-Wire
Resistive Touchscreen Controller with Proximity Sensing
11 I2C INTERFACE
11.1
Introduction
The chip is a read-write slave-mode I2C device and complies with the Philips I2C standard Version 2.1 dated
January, 2000. The chip has a few user-accessible internal 8-bits registers to set the various parameters of
operation (Cf. §12 for detailed configuration registers description). The I2C interface has been designed for
program flexibility, in that once the slave address has been sent to the chip enabling it to be a slave
transmitter/receiver, any register can be written or read independently of each other. The start and stop
commands frame the data-packet and the repeat start condition is allowed if necessary.
2 lines are used to exchange data between an external master host and the slave device:
SCL : Serial CLock
SDA : Serial DAta
Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by
the chip. The chip is not CBUS compatible and can operate in standard mode (100kbit/s) or fast mode
(400kbit/s).
11.2
I2C Address
On the QFN package an ADDR pin is made available to select between the two pre-programmed I2C addresses
of the device. On the CSP package ADDR is internally connected to ground.
This is illustrated in table below.
Package
ADDR
Address
Description
0
0x48 (1001000)
First I2C address
QFN
1
0x49 (1001001)
Second I2C address
CSP
0
0x48 (1001000)
First (and unique) I2C address
Table 8 – I2C Address
Please note that upon request, a custom I2C Address can be pre-programmed by Semtech.
11.3
Write Register
The I2C write register sequence is given in figure below. After the start condition [S], the chip slave address
(SA) is sent, followed by an eighth bit (W=‘0’) indicating a write. The chip then acknowledges [A] that it is being
addressed, and the host sends a CR byte consisting in ‘00’ followed by the chip register address (RA). The chip
acknowledges [A] and the host sends the appropriate data byte (WD0) to be written.
Again the chip
acknowledges [A]. In case the host needs to write more data, a succeeding data byte will follow (WD1),
acknowledged by the slave [A]. This sequence will be repeated until the host terminates the transfer with the
stop condition [P].
Figure 52 – I2C Write Register
The register address increments automatically when successive data bytes (WD1...WDn) are supplied by the
host.
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