th May 2012 www.semtech.com 9 SX1501/SX1502/SX1503 4/8/16 Channel Lo" />
參數(shù)資料
型號(hào)： SX1502I087TRT
廠商： Semtech
文件頁(yè)數(shù)： 32/32頁(yè)
文件大?。?/td> 0K
描述： IC GPIO EXPANDER I2C 8CH 20QFN
產(chǎn)品培訓(xùn)模塊： Low Voltage GPIO Expander Family
標(biāo)準(zhǔn)包裝： 1
接口： I²C
輸入/輸出數(shù)： 8
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 1.2 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-UFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 20-QFN-UT（3x3）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 1359 (CN2011-ZH PDF)
其它名稱： SX1502I087DKR
WIRELESS & SENSING
Rev 11 – 16
th May 2012
www.semtech.com
9
SX1501/SX1502/SX1503
4/8/16 Channel Low Voltage GPIO
Symbol
Description
Conditions
Min
Typ
Max
Unit
tf
Fall time of both SDA and
SCL signals
-
20+0.1Cb
(7)
-
300
ns
tSU;STO
Set-up time for STOP
condition
-
0.6
-
s
tBUF
Bus free time between a
STOP and START condition
-
1.3
-
s
Cb
Capacitive load for each bus
line
-
400
pF
VnL
Noise margin at the LOW
level for each connected
device (including hysteresis)
-
0.1*VDDM
-
V
VnH
Noise margin at the HIGH
level for each connected
device (including hysteresis)
-
0.2*VDDM
-
V
Miscellaneous
RPULL
Programmable pull-up/down
resistors for IO[0-7]
-
60
-
k
VCC1,2 & VDDM = 5V
-
25
tPLD
PLD propagation delay
VCC1,2 & VDDM = 1.2V
-
500
ns
(1) Assuming no load connected to outputs and inputs fixed to VCC1,2 or GND.
(2) Can be increased in RegAdvanced register. Please refer to §2.2.1 for more details.
(3) All values referred to VIHMR min and VILM max levels.
(4) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to VIHMR min) to bridge the undefined region of
the falling edge of SCL.
(5) The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
(6) A Fast-mode I
2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t
SU;DAT
≥ 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max+ tSU;DAT = 1000 + 250
= 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.
(7) Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.
Table 5 – Electrical Specifications
2.2.1
Increasing I/O Sink and Source Current Capabilities (Boost Mode)
When bit 1 of RegAdvanced register is set, max IOH and IOL spec when VCC1,2 is below VBOOST can be
increased together with IDDM and ICC1,2 figures as described below.
Symbol
Description
Conditions
Min
Typ
Max Unit
Supply
VBOOST Low voltage boost threshold
-
2.0
2.6
-
V
VDDM = 5.5V (VCC1,2 < 2V)
-
150
250
A
IDDM
Main supply current
(I
2C inactive)
VDDM = 1.2V (VCC1,2 < 2V)
-
25
50
uA
VCC1 = 2V
-
250
550
SX1501/2
VCC1 = 1.2V
-
100
200
VCC1 = 2V
-
250
550
ICC1
I/O bank A supply current
SX1503
VCC1 = 1.2V
-
100
200
A
VCC2 = 2V
-
150
250
SX1502
VCC2 = 1.2V
-
50
150
VCC2 = 2V
-
250
450
ICC2
I/O bank B supply current
SX1503
VCC2 = 1.2V
-
100
200
A
I/Os set as Output
VCC1,2 >= VBOOST
-
8
IOH
High level output source
current for all I/Os
VCC1,2 < VBOOST
-
4
mA
VCC1,2 >= VBOOST
-
24
Low level output sink current
for the high sink I/Os
VCC1,2 < VBOOST
-
12
mA
VCC1,2 >= VBOOST
-
12
IOL
Low level output sink current
for the other I/Os
VCC1,2 < VBOOST
-
6
mA
NINT, NRESET
VDDM >= VBOOST
-
12
IOLM
Low level output sink current
for NINT, NRESET
VDDM < VBOOST
-
6
mA
Table 6 – Electrical Specifications in Boost Mode
Important: RegAdvanced register doesn’t affect any spec when VCC1 and VCC2 are above VBOOST.
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