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參數(shù)資料
| 型號(hào)： | SURELINK |
| 元件分類： | 參考電壓二極管 |
| 英文描述： | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| 中文描述： | 250 的低電流運(yùn)算，低反向泄露，低噪聲穩(wěn)壓二極管 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 140K |
| 代理商： | SURELINK |
SureLINK
Ultra160 Domain Validation
F E AT U R E S
( C o n t i n u e d )
Includes drive strength margining
and programmable REQ/ACK
skew test
Supported by industry
’
s only
Ultra160 SCSI bus expander
Separate SCSI target validation
Target-specific SCSI settings
Bus width
Data transfer mode/rate
Graphical User Interface (GUI)
for control and configuration
Event-initiated alerts
On-screen notification of SCSI
bus status
phases and augments the CRC feature of LSI Logic
’
s Ultra160 SCSI solutions.
Additionally, the SCSI BIOS component of SureLINK technology enables
improved boot reliability by assuring optimum data transfer rates and bus
widths through successive INQUIRY results.
A p p l i c a t i o n s
Servers
- Internet/Intranet network, video, e-mail, printing,
database management, etc.
Workstations
- CAD/CAM, industrial simulation, etc.
Host-attach for RAID and JBOD mass storage subsystems
- Anywhere data
access is the bottleneck
I n t e g r i t y - C h e c k i n g M e t h o d s
The advanced SureLINK technology provides software control that
enables LSI Logic
’
s Ultra160 SCSI controllers to perform domain validation
to verify successful Ultra160 transfers. Verifying Ultra160 processes is done
through integrity checking-that is, a means for assuring that the physical
layer is able to transfer data between the initiator and the target at the
negotiated speed and width. SureLINK technology provides all three levels
of integrity checking (as defined in the ANSI T10 SPI-3 Annex), unprecedented
in the Ultra160 SCSI arena:
Basic Domain Validation (Level 1)
- Detects transfer errors and thus
determines if the initiator/target connection can operate at the maximum
speed and width;
Enhanced Domain Validation (Level 2)
- Assesses the stress placed on the
physical layer when known data patterns are sent and received;
Margined Domain Validation (Level 3)
- Provides information on the amount
of margin in a given system.
L E V E L 1 : B A S I C D O M A I N VA L I D AT I O N
Basic domain validation is performed by first issuing two INQUIRY
commands with the timing parameters set to asynchronous and narrow. The
data that is returned by the INQUIRY is stored so it can be compared later.
Next, a second INQUIRY command is issued with the period and width set
to the desired transfer rate. This second INQUIRY data is then compared to
that of the first. If the data does not match, the initiator falls back to a lower
speed/width and tries the INQUIRY again. If the data does match, the
2
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| SURGE | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
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| SUU06N10-225L | TRANSISTOR | MOSFET | N-CHANNEL | 100V V(BR)DSS | 6.5A I(D) | TO-251 |
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| SV010001 | BODENBELAG FESTES VINYL 5.0M |
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