參數(shù)資料
型號(hào): STW5094AD/LF
廠商: STMICROELECTRONICS
元件分類(lèi): DAC
英文描述: SERIAL INPUT LOADING, 18-BIT DAC, PBGA36
封裝: 6 X 6 MM, 1.2 MM HEIGHT, TFBGA-36
文件頁(yè)數(shù): 51/52頁(yè)
文件大?。?/td> 596K
代理商: STW5094AD/LF
7/51
A6
DX
DOT
Transmit Data output: Data is shifted out on this pin during the assigned
transmit time slots. Elsewhere DX output is in the high impedance state.
In delayed and non-delayed normal frame sync modes, voice data byte
is shifted out from tristate output DX at the MCLK frequency on the
rising edge of MCLK, while in non-delayed reverse frame sync mode
voice data is shifted out on the falling edge of MCLK.
A5
DR
DI
Receive data input: Data is shifted in during the assigned Received time
slots In delayed and non-delayed normal frame sync modes voice data
byte is shifted in at the MCLK frequency on the falling edges of MCLK,
while in non-delayed reverse frame sync mode voice data byte is shifted
in on the rising edge of MCLK.
B5
FS
DI
Frame Sync input for Voice Mode: This signal is a 8
16kHz clock
which defines the start of the transmit and receive frames. Any of three
formats may be used for this signal: non delayed normal mode, delayed
mode, and non delayed reverse mode.
A4
MCLK
DI
Master Clock Input for Voice Mode. Can also be used as Master Clock in
Tone Only and FM Modes. The allowed clock frequencies are 512 kHz,
1.536 MHz, 2.048 MHz or 2.56 MHz. MCLK is the Voice Data Clock.
C5
AUXCLK
DI
Auxiliary Clock Input. Can be used as Master Clock in Tone Only and
FM Modes. Allowed clock frequencies are 512kHz, 1.536MHz,
2.048MHz or 2.56MHz.
E4
VCMHP
AO
VCM Driver Output. Can be used as common mode node for HPL and
HPR outputs.
C3
CAP2
AI
A capacitor must be connected between this node and Ground.
C2
VCCA
P
Power supply input for the analog section. VCC and VCCA can be
directly connected together for low cost applications.
D1
GNDA
P
Analog Ground: All analog signals are referenced to this pin. GND and
GNDA can be connected together for low cost applications.
F3
VCCP
P
Power supply input for the output drivers.
E3
GNDP
P
Power ground. Output drivers are referenced to this pin. GNDP and
GNDA must be connected together.
D3
GNDCM
P
Analog Ground connection. GNDCM can be connected to GNDA.
B4
VCC
P
Power supply input for the digital section.
B6
GND
P
Ground for the digital section
D4
VCCIO
P
Power supply Input for the Digital I
O pins.
Pin N°
Name
Type
Description
相關(guān)PDF資料
PDF描述
SU-1-B3 POWER TRANSFORMER, 1000 VA
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