參數(shù)資料
型號: STV9936PS
英文描述: 120MHZ ON SCREEN DISPLAY FOR MONITORS WITH 4 TRUE INDEPENDANT WINDOW DISPLAYS
中文描述: 120MHz的屏幕顯示的4真獨立的窗口監(jiān)測儀顯示展示
文件頁數(shù): 34/48頁
文件大小: 1004K
代理商: STV9936PS
General OSD Programming
STV9936P/S
34/48
Fast Blanking Output Polarity (FBLK output)
The output polarity of the FBLK pin is selected by bit FBLKPOL. The default value is 0.
7.5
Reset
Power On Reset
The digital core and the PLL are asynchronously reset at Power On.
Soft Reset
A soft reset is enabled by the RST bit.
RST = 1: The digital core is reset. All control registers, except PLL registers, are reset at the
same value as at power on reset.
It is not necessary to write RST = 0 to stop the reset. This bit is automatically cleared.
PLL Register Reset
The Pixel Clock Generator (VCO[1:0]) and Horizontal Resolution (HR[6:0]) bits are reset by the
RST_PLL bit.
RST_PLL
= 1: HR[6:0] and VCO[1:0] are reset to the same value as the power-on reset.
It is not necessary to write RST_PLL = 0 to stop the reset. This bit is automatically cleared.
Table 42: Fast Blanking Output Polarity Selection
FBLKPOL
Description
0
When OSD display, FBLK = 1
When active video, FBLK = 0
1
When OSD display, FBLK = 0
When active video, FBLK = 1
Table 43: FBLK Output Control
ENOSD
Bit
FBLKPOL
Bit
FBK Bit
FBLK Output
Display
1
0
0
0
Video
Default Value
1
0
0
1
OSD
1
0
1
1
OSD
Full Screen
1
1
0
0
OSD
FBLK Inverted
1
1
0
1
Video
1
1
1
0
OSD
Full Screen
0
0
x
0
Video
No OSD
0
1
x
1
Video
No OSD
Table 44: Reset
FWR
FAC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80h
06h
RST_PLL
RST
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