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參數(shù)資料
| 型號： | STV9429 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | High Speed Multisynch On-Screen Display for Monitor(用于監(jiān)視器的屏上顯示) |
| 中文描述： | 高速Multisynch屏幕的顯示器顯示（用于監(jiān)視器的屏上顯示） |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 559K |
| 代理商： | STV9429 |
FILTRE
%N
F
XTAL
VCO
N . F
XTAL
9
Figure 11 :
Analogic PLL
ALGO
%M
F
H-SYNC
%D
M . F
H-SYNC
err(n)
D(n)
N . F
XTAL
9
Figure 12 :
Digital PLL
FUNCTIONAL DESCRIPTION
(continued)
VI - PLL
The PLL function of the STV9427/28/29 provides
the internal pixel clock locked on the horizontal
synchro signal and used by the display processor
to generate the R, G, B and fast blancking signals.
It is made of 2 PLLs. The first one analogic (see
Figure 11), provides a high frequency signal locked
on the crystal frequency. The frequency multiplier
is given by :
N = 2
(FM[3:0] + 3)
Where FM[3:0] is the value of the FREQUENCY
MULTIPLIER register.
The second PLL, full digital (see Figure 12), pro-
vides a pixel frequency locked on the horizontal
synchro signal. The ratio between the frequencies
of these 2 signals is :
M = 12 x (LD[6:1] x 2 + 1)
Where LD[6:1] is the value of the LINE DURATION
register.
VI.1 - Programming of the PLL Registers
Frequency Multiplier
(@3FF8)
This register gives the ratio between the crystal
frequency and the high frequency of the signal
used by the 2
nd
PLL to provide, by division, the pixel
clock. The value of this high frequency must be
near to 200MHz (for example if the crystal is a
8MHz, the value of FM must be equal to 10) and
greater than 2.5 x (pixel frequency). The frequency
of VCO must stand within limits given below :
F
pxlmin
x 16
≥
F
VCO
≥
F
pxlmax
x 2.5
Initial Pixel Period
(@3FF7)
This register allows to increase the speed of the
convergence of the PLL when the horizontal fre-
quency changes (new graphic standart). The rela-
tionship between FM[3:0], PP[7:0], LD[6:1], f
HSYNC
and f
XTAL
is :
PP[7:0]
=
round
Locking Condition Time Constant
(@ 3FF5)
This register gives the constants AS[2:0] and
BS[2:0] used by the algo part of the PLL
(see Figure 11) to calculate, from the phase error,
err(n), the new value, D(n), of the division of the
high frequency signal to provide the pixel clock.
These two constants are used only in locking con-
dition, which is true, if the phase error is less than
a fixed value during at least, 4 scan lines. If the
phase error becomes greater than the fixed value,
the PLL is not in locking condition but in capture
process. In this case, the algo part of the PLL used
the other constants, AF[2:0] and BF[2:0], given by
the next register.
Capture Process Time Constant
(@ 3FF6)
The choice between these two time constants
(locking condition or capture process) allows to
decrease the capture process time by changing the
time response of the PLL.
8
2
(
FM[3:0]
+
3
)
F
XTAL
6
(
LD[6:1]
2
+
1
)
F
HSYNC
24
STV9427 - STV9428 - STV9429
16/20
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