參數(shù)資料
型號(hào): STV9427
廠商: 意法半導(dǎo)體
英文描述: HIGH SPEED MULTISYNCH ON-SCREEN DISPLAY FOR MONITOR
中文描述: 高速M(fèi)ULTISYNCH屏幕的監(jiān)視器顯示
文件頁(yè)數(shù): 6/20頁(yè)
文件大小: 558K
代理商: STV9427
FUNCTIONAL DESCRIPTION
The STV9427/28/29 display processor operation is
controlled by a host MCU via the I
2
C interface. It is
fully programmable through internal read/write reg-
isters and performs all the display functions by
generating pixels from data stored in its internal
memory. After the page downloading from the
MCU, the STV9427/28/29 refreshes screen by
its built in processor, without any MCU control
(access). In addition, the host MCU has a direct
access to the on chip 1Kbytes RAM during the
display of the current page to make any update
of its contents.
With the STV9427/28/29, a page displayed on the
screen is made of several strips which can be of 2
types : spacing or character and which are de-
scribed by a table of descriptors and character
codes in RAM. Several pages can be downloaded
at the same time in the RAM and the choice of the
current display page is made by programming the
DISPLAY CONTROL register.
I - Serial Interface
The 2-wires serial interface is an I
2
C interface. To
be connected to the I
2
C bus, a device must own its
slave address ; the slave address of the
STV9427/28/29 is BA (in hexadecimal).
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
1
1
1
0
1
I.1 - Data Transfer in Write Mode
The host MCU can write data into the
STV9427/28/29 registers or RAM.
To write data into the STV9427/28/29, after a start,
the MCU must send (Figure 4) :
- First, the I
2
C address slave byte with a low level
for the R/W bit,
- The two bytes of the internal address where the
MCU wants to write data(s),
- The successive bytes of data(s).
All bytes are sent MSB bit first and the write data
transfer is closed by a stop.
Each byte is synchronously transfered at each
HSYNC period.
I.2 - Data Transfer in Read Mode
The host MCU can read data from the
STV9427/28/29 registers, RAM or ROM.
To read data from the STV9427/28/29 (Figure 5),
the MCU must send 2 different I
2
C sequences. The
first one is made of I
2
C slave address byte with R/W
bit at low level and the 2 internal address bytes.
The second one is made of I
2
C slave address byte
with R/W bit at high level and all the successive
data bytes read at successive addresses starting
from the initial address given by the first sequence.
Each byte is synchronously transfered at each
HSYNC period. The first data byte, in read mode,
is available one Hsync period after the acknow-
ledge of the address byte.
SCL
SDA
R/W
A7
A6
A5
A4
A3
A2
A1
A0
-
-
A13
A12
A11
A10
A9
A8
I
2
C Slave Address
ACK
LSB Address
ACK
MSB Address
ACK
Start
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ACK
ACK
Data Byte 1
Data Byte 2
ACK
Data Byte n
Stop
SCL
SDA
9
Figure 4 :
MCU I
2
C Write Operation
SCL
SDA
R/W
A7
A6
A5
A4
A3
A2
A1
A0
I
2
C Slave Address
ACK
LSB Address
ACK
MSB Address
ACK
Start
-
-
A13 A12
A10
A10
A9
A8
Stop
SCL
SDA
R/W
D7
D6
D5
D4
D3
D2
D1
D0
I
2
C Slave Address
ACK
ACK
Data Byte n
ACK
Start
D7
D6
D5
D4
D3
D2
D1
D0
Stop
Data Byte 1
*
9
Note :
The first data bit out (D7) is valid after one scanline period.
Figure 5 :
MCU I
2
C Read Operation
STV9427 - STV9428 - STV9429
6/20
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