參數(shù)資料
型號: STV9420
廠商: 意法半導體
英文描述: MULTISYNC ON-SCREEN DISPLAY FOR MONITOR
中文描述: 多頻屏幕的監(jiān)視器顯示
文件頁數(shù): 6/16頁
文件大小: 228K
代理商: STV9420
FUNCTIONAL DESCRIPTION
The STV9420/21 display processor operation is
controlledby a host MCU via theI
2
C interface. Itis
fully programmable through 8 internal read/write
registers (12 for STV9421) and performs all the
display functions by generating pixels from data
storedin its internalmemory. After thepage down-
loading from the MCU, the STV9420/21refreshes
screen by its built in processor, without any MCU
control (access).In addition, the host MCU has a
direct access to the on chip 1Kbytes RAM during
the displayof thecurrent pageto make anyupdate
of its contents.
With the STV9420/21, a page displayed on the
screen is made of several strips which can be of 2
types : spacing or character and which are de-
scribed by a table of descriptors and character
codes in RAM. Several pages can be downloaded
at the sametime in the RAM and the choiceof the
current display page is made by programmingthe
CONTROL register.
I - Serial Interface
The 2-wires serial interface is an I
2
C interface. To
be connectedto the I
2
C bus,a devicemust ownits
slave address ; the slave address of the
STV9420/21is BA(in hexadecimal).
A6
1
A5
0
A4
1
A3
1
A2
1
A1
0
A0
1
R/W
I.1 - Data Transferin Write Mode
The hostMCU canwrite datainto the STV9420/21
registersor RAM.
Towrite datainto the STV9420/21,aftera start,the
MCUmust send(Figure 3) :
- First,the I
2
C address slave byte with a low level
for the R/W bit,
- The two bytes of the internal address where the
MCU wants to write data(s),
- The successivebytes of data(s).
All bytes are sent MS bit first and the write data
transfer is closed by a stop.
I.2 - Data Transferin Read Mode
The hostMCUcan readdatafromtheSTV9420/21
registers, RAM or ROM.
To read data from the STV9420/21(Figure 4), the
MCUmust send2 different I
2
C sequences.
The firstoneis madeof I
2
Cslaveaddressbytewith
R/W bit at low level and the 2 internal address
bytes.
The secondone is made ofI
2
C slave addressbyte
with R/W bit at high level and all the successive
data bytes read at successive addressesstarting
from the initialaddressgivenby thefirst sequence.
SCL
SDA
R/W
A7
A6
A5
A4
A3
A2
A1
A0
I
1
C SlaveAddress
ACK
LSB Address
ACK
MSB Address
ACK
Start
-
-
A13 A12 A10 A10 A9
A8
Stop
SCL
SDA
R/W
D7
D6
D5
D4
D3
D2
D1
D0
I
1
C SlaveAddress
ACK
ACK
Data Byte n
ACK
Start
D7
D6
D5
D4
D3
D2
D1
D0
Stop
Data Byte 1
9
Figure 4 :
STV9420/I
2
C ReadOperation
SCL
SDA
R/W
A7
A6
A5
A4
A3
A2
A1
A0
-
-
A13
A12
A11
A10
A9
A8
I
2
C Slave Address
ACK
LSB Address
ACK
MSB Address
ACK
Start
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ACK
ACK
Data Byte1
Data Byte 2
ACK
Data Byte n
Stop
SCL
SDA
9
Figure 3 :
STV9420/I
2
C Write Operation
STV9420 - STV9421
6/16
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