參數(shù)資料
型號(hào): STV9410
廠商: 意法半導(dǎo)體
英文描述: CRT AND LCD SEMI-GRAPHIC DISPLAY PROCESSOR
中文描述: CRT和LCD半圖形顯示處理器
文件頁(yè)數(shù): 13/25頁(yè)
文件大小: 262K
代理商: STV9410
TIMING DIAGRAM
DESIGNATION
COMMENTS
PIXEL CLOCK
Y OUTPUT
START
”HORT” MSB REG
”HORT” LSB REG
”HSYN” LSB REG
”HSYN” MSB REG
HSYN PULSE
0 Start
Margin
Active Area (320 pixels)
START
Margin
End of line
0
8pxlck Fixed
= (MG +1) x 8 x pxlck
= (L +1) x 8 x pxlck
= (SD + 1) x 2 x pxlck
= (SU + 1) x 2 x pxlck
0 = origin
DAC output
Crystal = 8MHz
pxlck = 125ns
9
Figure 8 :
Horizontal SynchronizationTiming
VideoValidationand Port Register
(PORT)
Internaladdress : 2FF7-2FF6 h
RESETvalue :00-00 h
(@ = RESETdefault configuration)
2FF7
@
VOE
0
-
0
-
0
-
0
-
0
-
0
TE
0
PV
0
2FF6
@
N7
0
N6
0
N5
0
N4
0
N3
0
N2
0
N1
0
N0
0
VOE
:
Video Output Enable
1 enable synchro & video outputs
0 disable synchro & video outputs @
(@ Output Y, C
, V
, R, G, B, I, POR,
and DF are grounded, Input SYNC IN is high
impedance)
Timer Enable
1 POR provides a square wave signal with a
period of 16 x N(7:0) x pxlck
0 POR output is PV bit @
Port Value
POR output value if TE=0 (@=0)
Square wave period on POR if TE=1 (@=0)
TE
:
PV
:
N(7:0)
:
BEWARE
The programmationof VERT, HORI, HSYN regis-
tersmust beconsistent.Toget aproperwork of the
controller, the following conditions must, in any
mode (CRTor LCD), be fulfiled :
- SU
SD
-
SU
+
1
4
- 2(MG + 1) +40
L
Line periodis :
- P
L
= [L(5:0) + 1] x 8 pxlck
- In LCD, MG(2:0) can be 0, then minimum Line
Period is P
L (min.)
= 43 x 8 pxlck
Frame period is :
- P
F
= [F(8:0) + 2] x P
L
- In LCD, using a 240 lines matrix, F(8:0) = 238,
then minimum frame is :
P
F (min.)
= 240 x 43 x 8 pxclk
Pixelperiod is :
P
Frame
[ F
(
8:0
) +
2
] [ L
(
5:0
) +
1] x 8
- In LCD, using a 240 lines matrix, and
< L and
SD
+
1
4
< L
- Pxclk =
MG(2:0)= 0, Pxclk =
P
Frame
240 x 43 x 8
Interlacedmode conditions:
-
SU
+
1
4
-
SU
+
1
4
and
SD
+
1
4
< L
and
SD
+
1
4
> (MG + 1) +42
STV9410
13/25
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