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參數(shù)資料
| 型號： | STV8164 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | +5 V, +5 V and Adjustable Triple-Voltage Regulator with Disable and Reset Functions |
| 中文描述： | 5伏，5伏和可調(diào)三禁用電壓調(diào)節(jié)器和復(fù)位功能 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 110K |
| 代理商： | STV8164 |
CIRCUIT DESCRIPTION
STV8164
6/11
3
CIRCUIT DESCRIPTION
The STV8164 is a triple-voltage regulator with Reset and Disable functions.
The three regulation parts are supplied from a single voltage reference circuit trimmed by zener
zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin
INPUT1 (V
IN1
), the second and third regulators will not work if pin INPUT1 is not supplied.
The output stages are designed using a Darlington configuration with a typical dropout voltage of
1.0 V.
The adjustable voltage of pin OUTPUT3 is defined by output bridge resistors (R1 and R2). The
values of these resistors are calculated to obtain, with the targeted value for pin OUTPUT3, the
VPROG voltage (2.0 V) on the median point connected to pin PROGRAM.
IMPORTANT:
In all applications, all three inputs must be polarized. If Outputs 2 or 3 are not used, the
corresponding inputs must be connected to Input 1.
The Disable circuit will switch off pins OUTPUT2 and OUTPUT3 if a voltage less than 0.8 V is
applied to pin DISABLE.
The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below V
OUT1
-0.25 V
(4.75 V Typ.), the "a" comparator (
Figure 2
) rapidly discharges the external capacitor (Ce) and the
reset output immediately switches to low. When the voltage at pin OUTPUT1 exceeds
V
OUT1
-0.175 V (4.825 V Typ.), the V
Ce
voltage increases linearly to the reference voltage (V
REF
=
2.5 V) corresponding to a Reset Pulse Delay (t
RD
) as shown in
Figure 3
.
Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second
comparator "b" has a large hysteresis (1.9 V).
3.1
Currents versus Maximum Power Limitation
The currents provided by the three outputs can reach 1.6 A. However, the power dissipation in the
STV8164 must be established so as not to activate the automatic thermal shutdown (T
J
= 150° C).
It is recommended not to have all three currents at their maximum value simultaneously.
For example, if T
AMB(MAX.)
= 70° C, the maximum power dissipation in the STV8164 will be (with
R
thJA
= 12 °C/W):
This means that the following conditions apply to input voltages and currents:
(V
IN1
- 5 V) x I
IO1
+ (V
IN2
- 5 V) x I
IO2
+ (V
IN3
- V
OUT3
) x I
IO3
< 5.8 W
t
RD
C
-------------------------
2.5V
×
10
μ
A
=
12
°
C W
–
C
----------------------------------
5.8W
=
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