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參數(shù)資料
| 型號： | STV7778S-1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 偏轉(zhuǎn)處理器多同步監(jiān)測 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 125K |
| 代理商： | STV7778S-1 |
PIN-OUT DESCRIPTION
Pin N°
1
2
Name
PLL2C
H-DUTY
Function
Second PLL Loop Filter
DC Control of Horizontal Drive Output Pulse Duty-cycle.
If this pin is grounded, the horizontal and vertical outputs are inhibited. By connecting a capacitor
on this pin a soft-start function may be realized on h-drive output.
Horizontal Flyback Input (Positive Polarity)
Horizontal Section Ground. Must be connected only to components related to H blocks.
Horizontal Section Reference Voltage. Must be filtered by capacitor to Pin 4
3
4
5
6
7
8
9
10
11
12
13
H-FLY
H-GND
H-REF
NC
NC
NC
NC
C0
R0
PLL1F
HLOCK-CAP
Horizontal Oscillator Capacitor. To be connected to Pin 4.
Horizontal Oscillator Resistor. To be connected to Pin 4.
First PLL Loop Filter. To be connected to Pin 4.
First PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the frequency change detected
on Pin13. When frequency is changing, a blanking pulse is generated on Pin 23, the duration of this
pulse is proportionnal to the capacitor on Pin 13. To be connected to Pin 4.
DC Control for Free Running Frequency Setting. Comming from DAC output or DC voltage
generated by a resistor bridge connected between Pin 5 and 4.
DC Control for Horizontal Centering
X-RAY Protection Input (with internal latch function)
TTL Horizontal Sync Input
Supply Voltage (12V Typical)
Ground
Horizontal Drive Output (emiter of internal transistor)
Horizontal Drive Output (open collector of internal transistor)
B+ PWM Regulator Output
Safety Blanking Output. Activated during frequency changes, when X-RAY input is triggered or
when VS is too low.
Vertical Section Signal Ground
Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
Vertical Section Reference Voltage
Vertical Sawtooth Generator Capacitor
DC Control of Vertical S Shape Amplitude
DC Control of Vertical S Centering
Vertical Ramp Output (with frequency independant amplitude and S-correction)
DC Control of Vertical Amplitude Adjustment
Vertical Position Reference Voltage Output Temperature Matched with V-AMP Output
DC Control of Vertical Position Adjustment
Vertical TTL Sync Input
TTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input signal)
East/West Pincushion Correction Parabola Output
DC Control of East/West Pincushion Correction Amplitude
DC Control of Keystone Correction
DC Control of B+ Adjustment
Regulation Input of B+ Control Loop
B+ Error Amplifier Output for Frequency Compensation and Gain Setting
Sensing of External B+ Switching Transistor Emiter Current
14
FH-MIN
15
16
17
18
19
20
21
22
23
H-POS
XRAY-IN
H-SYNC
V
CC
GND
H-OUTEM
H-OUTCOL
B+ OUT
SBLK OUT
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VGND
VAGCCAP
V
REF
VCAP
VS-AMP
VS-CENT
VOUT
V-AMP
V
DCOUT
V-POS
VSYNC
PLL1INHIB
E/WOUT
E/W-AMP
KEYST
B+ ADJ
REGIN
COMP
I
SENSE
7
STV7778S
3/11
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