參數(shù)資料
型號(hào)： STV1601A
廠商： 意法半導(dǎo)體
英文描述： SERIAL INTERFACE TRANSMISSION ENCODER
中文描述： 串行接口傳輸編碼器
文件頁(yè)數(shù)： 12/17頁(yè)
文件大?。?/td> 244K
代理商： STV1601A
3. PLL block
PARALLELCLOCK INPUT CONTROL
PLL, PLL lock detectionand the various blocks of
the serial output control are shown in Figure 13.
When TN1 is connected to GND (set High), the
parallel clock input is disabled.
The VCO turns to free running conditions and its
frequencycan be adjustedthrough FV.
This frequencydecreaseswhen the resistor value
between FV and V
EE
is reduced. Oscillation fre-
quency monotoring is performed through PCK
which delivers a frequencydivided byten.
When PLL is locked, PLL and PCX input signal
phases are nearly matched. The RC network con-
nected to TN1, temporarily, disables the parallel
clockin orderto avoid mislocking problems.
VCO oscillationfrequency range selection is avail-
able through RSE ; High : from 140 to 270MHz ;
Low : from100 to 145MHz.
TRP (Pin 34) is the phase comparator output. To
minimize jitter, a trap circuit, consisting in a serial
tuned circuit at parallel clock frequency can be
used.
Figure13 :
PLLand SerialOutput ControlBlock
PLL LOCK DETECTION
The LSTsignal is generatedby latching theincom-
ing parallelclock by the internalone (which is 1/10
of the VCO frequency).LST is usedas a PLL lock
detection signalandalsocontrolsthe serialoutput.
If the parallel clock input is disabled (by means of
TN1), LST turns Low and the serial output is dis-
abled as described in the previous section (SX
(Pin 3) = High, SY (Pin 4) = Low).
If the serial output has to be disabled while no
parallel clock input is provided, PCX must be set
Low and PCYmust beset High.
4. Sync word
Toconvert serial data back to parallel, insertionof
some timing reference data indicating the parallel
data word boundary in the serial data is needed.
This,called TRS (Timing Reference Signal) in the
digital interface format, consists of the three con-
secutivewords 3FFH, 000H,000H.
Conversionto 10-bit TRS from 8-bit(TRS)
8-bit parallel data
8-bit paralleldata can beconvertedinto 10-bitdata
by using the 8th bit as the MSB and by setting the
2 LSBs at logicalstates as shownin Figure14.
LST
SX
SY
Serial Clock
PCY PCX
TN1
FV
TRP
RSE
PCK
PHASE
COMPARATOR
VCO
1/10 DIVIDER
NRZTo NRZI
CONVERSION
SCRAMBLER
Q
D
Q
D
”0”
1
STV1601A
12/17
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