參數(shù)資料
型號(hào): STR71XF
廠商: 意法半導(dǎo)體
英文描述: ARM7TDMI? 16/32-BIT MCU WITH FLASH, USB, CAN 5 TIMERS, ADC, 10 COMMUNICATIONS INTERFACES
中文描述: ARM7TDMI的? 16/32位微控制器5定時(shí)器,ADC和10 COMMUNICAT離子接口與閃存,USB,可以
文件頁(yè)數(shù): 11/49頁(yè)
文件大?。?/td> 678K
代理商: STR71XF
STR71xF - INTRODUCTION
11/49
Legend / Abbreviations for
Table 3
:
Type:
I = input, O = output, S = supply, HiZ= high impedance,
In/Output level: C = CMOS 0.3V
DD
/0.7V
DD
C
T
= CMOS 0.8V / 2V with input trigger
T
T
= TTL 0.3V
DD
/0.7V
DD
with input trigger
C/T = Programmable levels: CMOS 0.3V
DD
/0.7V
DD
or TTL 0.8V / 2V
Port and control configuration:
– Input:
pu/pd= software enabled internal pull-up or pull down
pu= in reset state, the internal 100k
weak pull-up is enabled.
pd = in reset state, the internal 100k
weak pull-down is enabled.
– Output:
OD = open drain
(logic level)
PP = push-pull
T = true OD, (P-Buffer and protection diode to V
DD
not implemented), 5V tolerant.
Table 3. STR710 Pin Description
Pin n°
Pin Name
T
I
1
Input
Output
A
Main
function
(after
reset)
Alternate function
T
B
i
C
O
P
1
A1
P0.10/U1.RX/
U1.TX/
SC.DATA
I/O pd C
T
X 4mA T
Port
0.10
UART1: Receive
Data input
Note:
This pin may be used for Smartcard
DataIn/DataOut or single wire UART (half du-
plex) if programmed as Alternate Function
Output. The pin will be tri-stated except when
UART transmission is in progress
External Memory Interface: Active low read signal for
external memory. It maps to the OE_N input of the ex-
ternal components.
UART1: Transmit data
output.
2
B2
RD
O
X
3
C2
P0.11/
BOOT.1/
U1.TX
I/O pd C
T
4mA X
X
Port
0.11
Select Boot Con-
figuration input
UART1: Transmit data
output.
4
C3
P0.12/SC.CLK
I/O pd C
T
4mA
Port
0.12
Ground voltage for digital I/Os
Supply voltage for digital I/Os
External Memory Interface: Select Memory
Bank 0 output
Note:
This pin is forced to output mode at re-
set to allow boot from external memory
External Memory Interface: Select Memory
Bank 1 output
Port
0.13
Data input
Port
0.14
data output
External Memory Interface: Select Memory
Bank 3 output
Smartcard reference clock output
5
6
D1
D2
V
SS
V
33
S
S
7
B1
P2.0/CS.0
I/O pu C
T
8mA X
X
Port 2.0
8
C1
P2.1/CS.1
I/Opu
C
T
8mA X
X
Port 2.1
9
D3
P0.13/U2.RX/
T2.OCMPA
P0.14/U2.TX/
T2.ICAPA
I/O pu C
T
X 4mA X
X
UART2: Receive
Timer2: Output Compare
A output
Timer2: Input Capture A
input
10
D4
I/O pu C
T
4mA X
X
UART2: Transmit
11
E1
P2.2/CS.2
I/Opu
C
T
8mA X
X
Port 2.2
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