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參數(shù)資料
| 型號： | STP1080ABGA-83 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 124K |
| 代理商： | STP1080ABGA-83 |
193
Companion Device for 167/200 MHz UltraSPARC-I Systems
UltraSPARC-I Data Buffer (UDB-I)
STP1080A
July 1997
TECHNICAL OVERVIEW
Data Buffering
UltraSPARC-I can have multiple outstanding request types, and be responding to multiple request types from
the Interconnect (receiving interrupts, delivering snoop data). However, except for noncacheable stores,
UltraSPARC-I can have only one outstanding request of each type. ‘Outstanding” implies that the address is
driven to the interconnect, but not the data.
There is storage for 1 64-byte external cache line. Eight outstanding noncacheable stores are allowed (16-bytes
of data due to compression) using the full interconnect bandwidth of 1 per interconnect cycle).
64-byte Buffers
64-byte buffers are provided for READs from the DataBus, and for SNOOPs and Writebacks from the
EcacheBus.
16-byte Buffers
The UDB can hold data for 8 noncacheable stores in progress.This store data comes from UltraSPARC-I’s store
buffer.
8-byte Buffers
Two interrupts, each consisting of three 64-bit packets, are also buffered in UDB. One buffer holds data going
from the cpu to the UPA, while the other holds data going from the UPA to the cpu.
Sub-Block Ordering
The UDB delivers and receives 16-byte subblocks in desired-word-rst order. Subsequent blocks are deliv-
ered in order, wrapping to the beginning of the block, if necessary. UDB does no data re-ordering.
All 64-byte write-backs from UltraSPARC-I are delivered starting with subblock 0.Data returned for snoops is
desired subblock rst also. The UDB chips supply pending CopyBack data in the correct order for a snoop.
ECC/Parity
ECC is 8 bits per 64 data bits. It is one of the single-error correcting, double error (and nibble-error) detecting
codes. The implementation has separate trees for ECC checking and correcting. Correctable errors are xed in
the same cycle as they are detected. The UDB will log the syndrome for the error (to help in diagnosing
multi-bit errors). There are some CSR read/write registers for enabling/disabling ECC. (accessible through
special ASI load/stores). There are two trap modes:
1. Trap on any ECC error
2. Trap on non-correctable ECC error
TABLE 1: Mondo Vector Format
Component
Interrupt _0
(Cycle 1)
Interrupt_1
(Cycle 2)
Interrupt_2
(Cycle 3)
Interrupt_3
(Cycle 4)
UDB_h
Data0
Data1
Data2
xxxxxx
UDB_l
xxxxxx
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