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參數(shù)資料
| 型號： | STKM2000 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2 u/2 POLY/2 METAL BiCMOS MIXED ANALOG-DIGITAL STANDARD CELLS |
| 中文描述： | 2單位/ 2滌綸/ 2金屬的BiCMOS混合模擬，數(shù)字標(biāo)準(zhǔn)細(xì)胞 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 111K |
| 代理商： | STKM2000 |
CAD SUPPORT: A.D.S.
(Analog Design System)
SGS-THOMSON Microelectronics has introduced
a sophisticated CAD approach to reduce the
development leadtime and to increase design
flexibility and safety.
Programmable cells in the library are defined as:
G
alternative cell or,
G
adjustable cell or,
G
telescopic cell or,
G
parametrisable cell
Some specific parts of the design are automatically
handled by an analog design manager, in order to:
G
reduce capture errors
G
make unexperienced designer’s task easier
G
improve schematics lisibility
G
check electrical design rules (Analog or Digital)
The Analog Design manager takes into account:
G
transconductance block generation
G
automatic cell biasing
G
unconnected pins and power down processing
G
multipower supplies processing
A major step has been made with the introduction
of function generator and compiler approaches to
improve design automation and design efficiency.
Operational amplifier generator
From a generic symbol and some properties,
several parameters of the amplifier will be adjusted:
G
Biasing current which controls major parameters
of amplifier (gain-bandwidth, slew rate, power
consumption).
G
Frequency compensation which allows to adjust
and optimize the dynamic parameters versus the
capacitive and resistive load.
G
Power down capabilities.
G
Supply voltage of the cell.
A specific software manages all these properties
and automatically updates all libraries included in
the design flow: macro models and transistor level
models, footprint, GDS2 layout, LVS netlist.
Figure 3:
Analog Design System (A.D.S.) flow
Digital Analog
Symbols
Schematic
Capture
Data Base
Filter Compiler
DIGITAL
Generator
D
Netlist
Extractor
Analog Generator
G
G
Programmable Cells
Generation
G
Behavioral
Models
Top Level
Simulation
SABER
Digital
Models
D
G
Transistor
Models
Place & Route
Cells Boxes
G
Analog
Simulation
ST SPICE
Digital
Simulation
HILO 3
Back Annotation
GDSII File
DRC/LVS
Cells
Layout
G
PG Tape
STKM2000 SERIES
4/10
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