參數(shù)資料
型號(hào): STK16C88-3WF35I
元件分類: SRAM
英文描述: 32K X 8 NON-VOLATILE SRAM, 35 ns, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁(yè)數(shù): 8/13頁(yè)
文件大小: 341K
代理商: STK16C88-3WF35I
4
Jan, 2008
Document Control #ML0019 Rev 2.0
STK16C88-3
SRAM READ CYCLES #1 & #2
(VCC = 3.0V-3.6V)
Note f:
W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g:
I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h:
Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
SRAM READ CYCLE #2: E and G Controlledf
NO.
SYMBOLS
PARAMETER
STK16C88-3-35
UNITS
#1, #2
Alt.
MIN
MAX
1
tELQV
tACS
Chip Enable Access Time
35
ns
2
tAVAV
ELEH
tRC
Read Cycle Time
35
ns
3
tAVQV
tAA
Address Access Time
35
ns
4
tGLQV
tOE
Output Enable to Data Valid
15
ns
5
tAXQX
tOH
Output Hold after Address Change
5
ns
6
tELQX
tLZ
Chip Enable to Output Active
5
ns
7
tEHQZ
tHZ
Address Change or Chip Disable to Output Inactive
13
ns
8
tGLQX
tOLZ
Output Enable to Output Active
0
ns
9
tGHQZ
tOHZ
Output Disable to Output Inactive
13
ns
10
tELICCH
tPA
Chip Enable to Power Active
0
ns
11
tEHICCL
d, e
tPS
Chip Disable to Power Standby
35
ns
DATA VALID
tAXQX
tAVQV
DQ (DATA OUT)
ADDRESS
tAVAV
tELQX
STANDBY
DATA VALID
tGLQX
tGLQV
DQ (DATA OUT)
E
ADDRESS
tELEH
G
ICC
ACTIVE
tELQV
tELICCH
tEHICCL
tEHQZ
tGHQZ
3
tAVQV
27
tAVEL
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