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參數(shù)資料
| 型號： | ST95P08M6TR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | EEPROM |
| 英文描述： | 8 Kbit Serial SPI EEPROM with Positive Clock Strobe |
| 中文描述： | 8千位的SPI EEPROM，帶有正時鐘選通 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 119K |
| 代理商： | ST95P08M6TR |
C
Q
AI01072B
S
D
HOLD
tCLHX
tHXCH
tCLHX
tHHQX
tHLQZ
Figure 7. Hold Timing
Write Protect (W). This pin is for hardware write
protect. When W is low, non-volatile writes to the
ST95P08 are disabled but any other operation
stays enabled. When W is high, all operations
including non-volatile writes are available. W going
low at any time before the last bit D0 of the data
stream will reset the write enable latch and prevent
programming. No action on W or on the write
enable latch can interrupt a write cycle which has
commenced.
Hold (HOLD). The HOLD pin is used to pause
serial communications with a ST95P08 without
resetting the serial sequence. To take the Hold
condition into account, the product must be se-
lected (S = 0). Then the Hold state is validated by
a high to low transition on HOLD when C is low. To
resume the communications, HOLDis brought high
when C is low. During Hold condition D, Q, and C
are at a high impedance state.
When the ST95P08 is under Hold condition, it is
possible to deselect it. However, the serial commu-
nications will remain paused after a reselect, and
the chip will be reset.
OPERATIONS
All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
the chip select (S) goes low. Prior to any operation,
a one-byte instruction code must be entered in the
chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input
(C). To enter an instruction code, the product must
have been previously selected (S = low). Table 7
shows the instruction set and format for device
operation. When an invalid instruction is sent (one
not contained in Table 7), the chip is automatically
deselected. For operations that read or write data
in the memory array, bit 3 of the instruction is the
MSB of the address, otherwise, it is a don’t care.
Write Enable (WREN) and Write Disable (WRDI)
The ST95P08 contains a write enable latch. This
latch must be set prior to every WRITE or WRSR
operation. The WREN instruction will set the latch
and the WRDI instruction will reset the latch. The
latch is reset under all the following conditions:
– W pin is low
– Power on
– WRDI instruction executed
– WRSR instruction executed
– WRITE instruction executed
As soon as the WREN or WRDI instruction is
received by the ST95P08, the circuit executes the
instruction and enters a wait mode until it is dese-
lected.
7/16
ST95P08
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