參數(shù)資料
型號(hào)： ST92T163N4B1L
英文描述： 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS. 20K ROM. 2K RAM. I 2 C. SCI. & MFT
中文描述： 16位產(chǎn)品全速USB微控制器，16終點(diǎn)復(fù)合設(shè)備。 20,000光盤(pán)。 2K的RAM。余2長(zhǎng)脊髓損傷。
文件頁(yè)數(shù)： 173/230頁(yè)
文件大?。?/td> 2743K
代理商： ST92T163N4B1L
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ST92163 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
INTERRUPT/DMA PRIORITY REGISTER (IDPR)
R249 - Read/Write
Reset value: undefined
Bit 7 =
AMEN
:
Address Mode Enable.
This bit, together with the AM bit (in the CHCR reg-
ister), decodes the desired addressing/9th data
bit/character match operation.
In Address mode the SCI monitors the input serial
data until its address is detected
Note:
Upon reception of address, the RXAP bit (in
the Interrupt Status Register) is set and an inter-
rupt cycle can begin. The address character will
not be transferred into the Receiver Buffer Regis-
ter but all data following the matched SCI address
and preceding the next address word will be trans-
ferred to the Receiver Buffer Register and the
proper interrupts updated. If the address does not
match, all data following this unmatched address
will not be transferred to the Receiver Buffer Reg-
ister.
In any of the cases the RXAP bit must be reset by
software before the next word is transferred into
the Buffer Register.
When AMEN is reset and AM is set, a useful char-
acter search function is performed. This allows the
SCI to generate an interrupt whenever a specific
character is encountered (e.g. Carriage Return).
Bit 6 =
SB
:
Set Break
.
0: Stop the break transmission after minimum
break length.
1: Transmit a break following the transmission of all
data in the Transmitter Shift Register and the
Buffer Register.
Note:
The break will be a low level on the transmit-
ter data output for at least one complete word for-
mat. If software does not reset SB before the min-
imum break length has finished, the break condi-
tion will continue until software resets SB. The SCI
terminates the break condition with a high level on
the transmitter data output for one transmission
clock period.
Bit 5 =
SA
:
Set Address
.
If an address/9th data bit mode is selected, SA val-
ue will be loaded for transmission into the Shift
Register. This bit is cleared by hardware after its
load.
0: Indicate it is not an address word.
1: Indicate an address word.
Note:
Proper procedure would be, when the
Transmitter Buffer Register is empty, to load the
value of SA and then load the data into the Trans-
mitter Buffer Register.
Bit 4 =
RXD
:
Receiver DMA Mask
.
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
receiver End of Block interrupt can occur.
0: Disable Receiver DMA request (the RXDP bit in
the S_ISR register can request an interrupt).
1: Enable Receiver DMA request (the RXDP bit in
the S_ISR register can request a DMA transfer).
Bit 3 =
TXD
:
Transmitter DMA Mask
.
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
transmitter End Of Block interrupt can occur.
0: Disable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request an interrupt).
1: Enable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request a DMA trans-
fer).
Bit 2:0 =
PRL[2:0]
:
SCI Interrupt/DMA Priority bits
.
The priority for the SCI is encoded with
(PRL2,PRL1,PRL0). Priority level 0 is the highest,
while level 7 represents no priority.
When the user has defined a priority level for the
SCI, priorities within the SCI are hardware defined.
These SCI internal priorities are:
7
0
AMEN
SB
SA
RXD
TXD
PRL2
PRL1
PRL0
AMEN
0
0
AM
0
1
Address interrupt if 9th data bit = 1
Address interrupt if character match
Address interrupt if character match
and 9th data bit =1
Address interrupt if character match
with word immediately following Break
1
0
1
1
Receiver DMA request
Transmitter DMA request
Receiver interrupt
Transmitter interrupt
highest priority
lowest priority
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參數(shù)描述
ST92T163R4T1 功能描述:8位微控制器 -MCU OTP EPROM 20K USB/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST92T196/JAP 制造商:STMicroelectronics 功能描述:
ST92T96N9B1/AIN 制造商:STMicroelectronics 功能描述:
ST-930 制造商:UNBRANDED 功能描述:MULTIMETER DIGITAL BARGRAPH
ST93003 功能描述:兩極晶體管 - BJT Hi Vltg FAST SWITCH PNP Pwr TRANSISTOR RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產(chǎn)品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2
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