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參數(shù)資料
| 型號： | ST92R195B |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | ROMLESS HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
| 中文描述： | 無ROM HCMOS微控制器屏幕顯示和圖文電視數(shù)據(jù)限幅器 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 109K |
| 代理商： | ST92R195B |
14/18
ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
(Cont’d)
EXTERNAL MEMORY INTERFACE TIMING TABLE
(
V
DD
= 5V +/-10%;
T
A
= 0 to 70
°
C; unless otherwise specified))
TpC is the INTCLK clock period.
SPI TIMINGTABLE
(
V
DD
= 5V +/-10%;
T
A
= 0 to 70
°
C; Cload= 50pF)
(1) TpC is the OSCIN clock period; TpMC is the “Main Clock Frequency” period.
SKEW CORRECTOR TIMING TABLE
(
V
DD
= 5V +/-10%,
T
A
= 0 to 70
°
C, unless otherwise specified)
(*) TheOSD jitter is measured from leading edgeto leading edge of a single character row on consecutive TVlines. The value is an envelope
of 100 fields
Symbol
Parameter
Value
Unit
typ
max
T
wDSR
T
wDSW
T
dDSR
(DR)
T
hDR
(DS)
T
dDS
(A)
T
hDS
(AS)
T
sRW
(AS)
T
dDSR
(RW)
T
dDW
(DSW)
T
hDS
(DW)
T
dA
(DR)
DSN low level pulse width (read)
DSN low level pulse width (write)
DSN
↓
to data valid delay
Data to DSN
↑
hold time
DSN
↑
to address active delay
DSN
↑
to ASN
↓
delay
R/WN setup time before ASN
↑
DSN
↑
to R/WN and address not valid delay
Write data valid to DSN
↓
delay (write)
Data hold time after DSN
↑
(write)
Address valid to data valid delay (read)
TpC*(1/2+WDS)-6
TpC*(1/2+WDS)-6
TpC*(1/2+WDS)-16
0
TpC/2
TpC/2 + 6
TpC*(1/2 + WAS) - 8
TpC/2
0
TpC/2
TpC*(3/2+WDS+WAS)-14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
Condition
Value
Unit
min
tbd
max
T
sDI
T
hDI
T
dOV
T
hDO
T
wSKL
T
wSKH
Input Data Set-up Time
Input Data Hold Time
SCK to Output Data Valid
Output Data Hold Time
SCK Low Pulse Width
SCK High Pulse Width
ns
ns
ns
ns
ns
ns
(1)
OSCIN/2 as internal Clock
1INTCLK
+100ns
tbd
tbd
tbd
tbd
Symbol
Parameter
Conditions
max
Value
5*
Unit
T
jskw
Jitter on RGB output
36 MHz Skew corrector clock frequency
ns
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