參數(shù)資料
型號(hào): ST90T158M9LVQ1
廠(chǎng)商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, OTPROM, 14 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, QFP-80
文件頁(yè)數(shù): 178/190頁(yè)
文件大小: 1152K
代理商: ST90T158M9LVQ1
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI)
REGISTER DESCRIPTION (Cont’d)
EXTERNAL MEMORY REGISTER 2 (EMR2)
R246 - Read/Write
Register Page: 21
Reset value: 0000 1111 (0Fh)
Bit 7 = Reserved.
Bit 6 = ENCSR:
Enable Code Segment Register.
This bit affects the ST9 CPU behavior whenever
an interrupt request is issued.
0: The CPU works in original ST9 compatibility
mode concerning stack frame during interrupts.
For the duration of the interrupt service routine,
ISR is used instead of CSR, and the interrupt
stack frame is identical to that of the original
ST9: only the PC and Flags are pushed. This
avoids saving the CSR on the stack in the event
of an interrupt, thus ensuring a faster interrupt
response time. The drawback is that it is not
possible for an interrupt service routine to per-
form inter-segment calls or jumps: these instruc-
tions would update the CSR, which, in this case,
is not used (ISR is used instead). The code seg-
ment size for all interrupt service routines is thus
limited to 64K bytes.
1: If ENCSR is set, ISR is only used to point to the
interrupt vector table and to initialize the CSR at
the beginning of the interrupt service routine: the
old CSR is pushed onto the stack together with
the PC and flags, and CSR is then loaded with
the contents of ISR. In this case, iret will also re-
store CSR from the stack. This approach allows
interrupt service routines to access the entire
4Mbytes of address space; the drawback is that
the interrupt response time is slightly increased,
because of the need to also save CSR on the
stack. Full compatibility with the original ST9 is
lost in this case, because the interrupt stack
frame is different; this difference, however,
should not affect the vast majority of programs.
Bit 5 = DPRREM:
Data Page Registers remapping
0: The locations of the four MMU (Memory Man-
agement Unit) Data Page Registers (DPR0,
DPR1, DPR2 and DPR3) are in page 21.
1: The four MMU Data Page Registers are
swapped with that of the Data Registers of ports
0-3.
Refer to Figure 43
Bit 4 = MEMSEL: Memory Selection.
Warning: Must be set by the user when using the
external memory interface (Reset value is 0)
.
Bit 3:2 = LAS[1:0]:
Lower memory address strobe
stretch.
These two bits contain the number of wait cycles
(from 0 to 3) to add to the System Clock to stretch
AS during external lower memory block accesses
(MSB of 22-bit internal address=0). The reset val-
ue is 3.
70
-
ENCSR DPRREM
MEM
SEL
LAS1
LAS0
UAS1
UAS0
9
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ST90T158M9LVQ6 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-Bit Microcontroller
ST90T158M9LVT1 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM
ST90T158M9LVT6 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY
ST90T158M9Q6 功能描述:8位微控制器 -MCU Flash 64K SPI/2xSCI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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