參數(shù)資料
型號(hào): ST7PLITE05Y0B6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP16
封裝: 0.300 INCH, PLASTIC, DIP-16
文件頁(yè)數(shù): 47/125頁(yè)
文件大小: 1956K
代理商: ST7PLITE05Y0B6
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ST7LITE0x, ST7LITESx
28/125
7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 11.2.1 on page 54 for further details.
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
Active Phase depending on the RESET source
256 CPU clock cycle delay
RESET vector fetch
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilise and ensures that recovery has tak-
en place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of tSTARTUP (see
Figure 14. RESET Sequence Phases
Figure 15.Reset Block Diagram
RESET
Active Phase
INTERNAL RESET
256 CLOCK CYCLES
FETCH
VECTOR
RESET
RON
VDD
INTERNAL
RESET
PULSE
GENERATOR
FILTER
Note 1: See “Illegal Opcode Reset” on page 79. for more details on illegal opcode reset conditions.
LVD RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET 1)
1
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