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參數(shù)資料
| 型號： | ST7PLITE02Y0B6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 53/125頁 |
| 文件大?。?/td> | 1956K |
| 代理商： | ST7PLITE02Y0B6 |
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ST7LITE0x, ST7LITESx
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8.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 12.2.1 on page 79 for further details.
8.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
ates a static reset when the VDD supply voltage is
below a VIT-(LVD) reference value. This means that
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is
lower than the VIT+(LVD) reference value for power-
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
–VIT+(LVD)when VDD is rising
–VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 18.
The voltage threshold can be configured by option
byte to be low, medium or high. See section 15.1
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-(LVD), the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD is an optional function which can be se-
lected by option byte. See section 15.1 on page
It allows the device to be used without any external
RESET circuitry.
If the LVD is disabled, an external circuitry must be
used to ensure a proper power-on reset.
It is recommended to make sure that the VDD sup-
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
Caution: If an LVD reset occurs after a watchdog
reset has occurred, the LVD will take priority and
will clear the watchdog flag.
Figure 18. Low Voltage Detector vs Reset
VDD
VIT+(LVD)
RESET
VIT-(LVD)
Vhys
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST7PLITE02Y0B6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7PLITE02Y0M6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7PLITE02Y0M6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7PLITE02Y0U6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7PLITE02Y0U6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
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