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| 型號(hào)： | ST7LITE09Y0M6 |
| 英文描述： | FUSE, FORK LIFT TRUCK, 250A; Current, fuse rating:250A; Voltage rating, DC:80V; Approval category:DIN 43560/1; Depth, external:20mm; Height:1mm; Length / Height, external:0.5mm; Width, external:82mm RoHS Compliant: Yes |
| 中文描述： | ST7LITE0。 ST7SUPERLITE - 8位微控制器單電壓閃存。數(shù)據(jù)EEPROM。 ADC的。定時(shí)器。的SPI |
| 文件頁(yè)數(shù)： | 49/122頁(yè) |
| 文件大?。?/td> | 1716K |
| 代理商： | ST7LITE09Y0M6 |
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ST7LITE0, ST7SUPERLITE
49/122
LITE TIMER
(Cont’d)
Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter after a rising or falling edge
is detected on the ICAP1 pin. When an input cap-
ture occurs, the ICF bit is set and the LTICR regis-
ter contains the MSB of the free-running up-
counter. An interrupt is generated if the ICIE bit is
set. The ICF bit is cleared by reading the LTICR
register.
The LTICR is a read only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
11.1.4 Low Power Modes
11.1.5 Interrupts
Note:
The TBF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
They generate an interrupt if the enable bit is set in
the LTCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
Figure 32. Input Capture Timing Diagram.
Mode
Description
No effect on Lite timer
(this peripheral is driven directly
by f
OSC
/32)
No effect on Lite timer
SLOW
WAIT
ACTIVE-HALT No effect on Lite timer
HALT
Lite timer stops counting
Interrupt
Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Exit
from
Active-
Halt
Timebase
Event
IC Event
TBF
TBIE
Yes
No
Yes
ICF
ICIE
Yes
No
No
04h
8-bit COUNTER
t
01h
f
OSC
/32
xxh
02h
03h
05h
06h
07h
04h
LTIC PIN
ICF FLAG
LTICR REGISTER
CLEARED
BY S/W
READING
LTIC REGISTER
4μs
(@ 8MHz f
OSC
)
f
CPU
07h
1
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