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參數(shù)資料
| 型號(hào)： | ST7FLITE19F1M6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CLUSTER PANEL,RJ-11 W/ (12) 4- |
| 中文描述： | 8位單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，4定時(shí)器，微控制器的SPI |
| 文件頁(yè)數(shù)： | 24/131頁(yè) |
| 文件大?。?/td> | 2046K |
| 代理商： | ST7FLITE19F1M6 |
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ST7LITE1
24/131
1
PHASE LOCKED LOOP
(Cont’d)
Figure 11. PLL Output Frequency Timing
Diagram
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
STARTUP
.
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC
PLL
) is reached after
a stabilization time of t
STAB
(see
Figure 11
and
13.3.4 Internal RC Oscillator and PLL
)
Refer to
section 7.6.4 on page 33
for a description
of the LOCKED bit in the SICSR register.
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 =
MCO
Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
Bit 0 =
SMS
Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
clock f
OSC
or f
OSC
/32.
0: Normal mode (f
CPU =
f
OSC
1: Slow mode (f
CPU =
f
OSC
/32)
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
Bits 7:0 =
CR[7:0]
RC Oscillator Frequency Ad-
justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
Note:
To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.
4/8 x
input
freq.
LOCKED bit set
t
STAB
t
LOCK
O
t
STARTUP
t
7
0
0
0
0
0
0
0
MCO
SMS
7
0
CR70 CR60 CR50 CR40 CR30 CR20 CR10
CR
0
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