參數(shù)資料
型號(hào)： ST7FLITE10
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI
中文描述： 8位單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，4定時(shí)器，微控制器的SPI
文件頁數(shù)： 40/131頁
文件大?。?/td> 2046K
代理商： ST7FLITE10
ST7LITE1
40/131
1
POWER SAVING MODES
(Cont’d)
9.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when ACTIVE-HALT is disabled
(see
section 9.5 on page 41
for more details) and
when the AWUEN bit in the AWUCSR register is
cleared.
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 35) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see
Fig-
ure 24
).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im-
mediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
sec-
tion 15.1 on page 121
for more details).
Figure 23. HALT Timing Overview
Figure 24. HALT Mode Flow-chart
Notes:
1.
WDGHALT is an option bit. See option byte sec-
tion for more details.
2.
Peripheral clocked with an external clock source
can still be active.
3.
Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
Table 5 Interrupt Mapping
for more details.
4.
Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when-
the CC register is popped.
5.
If the PLL is enabled by option byte, it outputs
the clock after a delay of t
STARTUP
(see
Figure 11
).
HALT
RUN
RUN
256 OR 4096 CPU
CYCLE DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[Active Halt disabled]
FETCH
VECTOR
RESET
INTERRUPT
3)
Y
N
N
Y
CPU
I BIT
OSCILLATOR
PERIPHERALS
2)
OFF
OFF
OFF
0
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
I BIT
OSCILLATOR
PERIPHERALS
ON
OFF
ON
X
4)
CPU
I BIT
OSCILLATOR
PERIPHERALS
ON
ON
ON
X
4)
256 OR 4096 CPU CLOCK
DELAY
5)
CYCLE
WATCHDOG
ENABLE
DISABLE
WDGHALT
1)
0
WATCHDOG
RESET
1
HALT
INSTRUCTION
(Active Halt disabled)
(AWUCSR.AWUEN=0)
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