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參數(shù)資料
| 型號： | ST755CN |
| 廠商： | 意法半導體 |
| 英文描述： | ADJUSTABLE INVERTING NEGATIVE OUTPUT CURRENT MODE PWM REGULATORS |
| 中文描述： | 可調(diào)式逆變負輸出電流模式PWM調(diào)節(jié)器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 80K |
| 代理商： | ST755CN |
ELECTRICALCHARACTERISTICS
(Refer to the test circuits, V
CC
= 5V, V
out
= -5.25 to -4.75V,
I
load
= 0mA, T
a
= T
min
to T
max
unless otherwise specified. Typical Value are referred at T
a
= 25
o
C)
Symbol
Parameter
Test Conditions
V
IN
Input Voltage
V
o
OutputVoltage
I
o
= 0mA to200 mA V
CC
= 4.5 to 6.2 V
I
o
OutputCurrent
V
CC
= 4.5 to 6.2 V T
a
= 0
o
C to 70
o
C
V
CC
= 4.5 to 6.2 V T
a
= -40
o
C to 85
o
C
V
CC
= 4 V
V
CC
= 2.7 V
I
SUPPLY
Supply Current (Including
Switching Current)
I
OFF
StandbyCurrent
No Load,
V
SHDN
=0V
I
SC
Short Circuit Current
V
o
Line Regulation
V
CC
= 4 to 6.2V
V
o
Load Regulation
I
o
= 0mA to200 mA
V
REF
Reference Voltage
T
a
= 25
o
C
V
REF
Reference Dritft
T
a
= T
min
toT
max
R
DSON
LX OnResistance
I
LEAK
LX Leakage Current
V
DS
= 10 V
I
SH
Shutdown Pin Current
V
il
Shutdown Input Low Threshold
V
ih
Shutdown Input High
Threshold
f
o
OscillatorFrequency
ν
Power Efficency
I
o
= 100 mA
CC
Compensation Pin Impedance
Do not overload or short the Output to Ground. If the above conditions are observerd, the device may be damaged.
Min.
2.7
Typ.
Max.
11
Unit
V
-5.25
-5
-4.75
V
V
out
= -5 V
V
out
= -5 V
200
175
275
175
125
mA
mA
mA
mA
No Load, V
SHDN
= V
CC
1.2
3.5
mA
10
100
μ
A
A
1.2
0.1
%/V
0.003
%/mA
1.18
1.25
1.32
V
50
ppm/
o
C
μ
A
μ
A
V
0.7
1
1
0.25
2
V
160
KHz
68
%
K
7.5
APPLICATION INFORMATION
The ST755 is an IC developed for voltage
conversion from an input voltage ranging from
+2.4V to 11V to a regulated adjustable negative
output limited by |V
out
|
≤
12.7V-V
IN
. The circuit
adopts a current-mode PWM control scheme to
achieve good efficiency , high stability and low
noise performance. The figure in the first page
shown the detailed block diagram of the device.
ST755 is realized in a BCD technologyin orderto
achieve high temperature stability, the best
REFERENCE precision , a very low quiescent
current and jitter free operations. The final stage
is built around a 0.7
- 2A P-Channel Power
MOS. A fraction of the output current is splitted
out for current detection.Internal clock frequency
is fixed to 160KHz. Error amplifier drives the
PWM comparator in order to keep 0V on the CC
input. So R
3
and R
4
resistors are calculated by
the following formulae R
4
= (|V
out
|/V
ref
)*R
3
(see fig
1). For R
3
can be choosen any value between
2K
and 20K
. Soft-Start (SS) input is a voltage
dependent-output current limit (see figure 9,
Switch Current Limit vs. SS Input Voltage). SS
pin is internally pulled to V
ref
through a 1.2 M
resistor. Applying an appropiate capacitor at SS
input is
possible to obtain a soft-start current
limitation during power up. Forcing Soft-Start(SS)
input to a lower voltage through a resistive
voltage driver (R
1
and R
2
), the maximum LX
curent limit can be lowered according the
diagram showed in figure 9. When SHDN input is
low, the total current consumption is reduced to
10
μ
A.
ST755
3/9
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