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參數(shù)資料
| 型號： | ST72T311J2T3S |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Hook-Up Wire; Conductor Size AWG:16; No. Strands x Strand Size:19 x 29; Jacket Color:Gray; Cable/Wire MIL SPEC:MIL-W-16878/1 Type B; Conductor Material:Copper; Conductor Plating:Tin; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes |
| 中文描述： | 8位8 16K的檢察官辦公室/存儲器，384?512字節(jié)的RAM，ADC的，水分散粒劑，脊髓損傷，SPI和2單片機定時器 |
| 文件頁數(shù)： | 70/100頁 |
| 文件大?。?/td> | 660K |
| 代理商： | ST72T311J2T3S |
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ST72E311 ST72T311
SERIAL PERIPHERAL INTERFACE
(Cont’d)
4.5.4.4 Write Collision Error
A write collision occurs when the software tries to
write tothe DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Write collisionscan occur both inmaster and slave
mode.
Note:
a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is alwayssynchronous with the MCU oper-
ation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
For this reason, the SS pin mustbe high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
In Master mode
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The SS pin signal must be always high on the
master device.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 41).
Figure 41. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SR
Read DR
Write DR
2nd Step
SPIF =0
WCOL=0
SPIF =0
WCOL=0
if no transfer has started
WCOL=1
if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
WCOL=0
Read SR
Read DR
Note:
Writing in DR register in-
stead of reading in it do not reset
WCOL bit
Read SR
OR
THEN
THEN
THEN
70
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72T311J2T6S | Hook-Up Wire; Conductor Size AWG:16; No. Strands x Strand Size:19 x 29; Jacket Color:White; Cable/Wire MIL SPEC:MIL-W-16878/1 Type B; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:No RoHS Compliant: Yes |
| ST72T311N2B6S | 8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS |
| ST72E751N9D1 | 8-BIT, 56-PIN MCU FOR MONITORS, WITH UP TO 60K ROM, 2K RAM, ADC, TIMER, IR, SYNC, PWM/BRM, DDC/DMA, I2C & SCI |
| ST72T751N9B1 | 8-BIT, 56-PIN MCU FOR MONITORS, WITH UP TO 60K ROM, 2K RAM, ADC, TIMER, IR, SYNC, PWM/BRM, DDC/DMA, I2C & SCI |
| ST7275-1 | 8-BIT, 56-PIN MCU FOR MONITORS, WITH UP TO 60K ROM, 2K RAM, ADC, TIMER, IR, SYNC, PWM/BRM, DDC/DMA, I2C & SCI |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72T311J2T6 | 功能描述:8位微控制器 -MCU OTP EPROM 8K SPI/I2C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72T311J2T6S | 制造商:STMicroelectronics 功能描述: |
| ST72T311J4B6 | 功能描述:8位微控制器 -MCU OTP EPROM 16K SPI/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72T311J4T6 | 功能描述:8位微控制器 -MCU OTP EPROM 16K SPI/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72T311J4T6S | 制造商:STMicroelectronics 功能描述: |
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