參數(shù)資料
型號: ST72T2311R7T7
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
中文描述: 8位嵌套中斷,EEPROM存儲器,模數(shù)轉(zhuǎn)換器,16位定時器,8位PWM藝術(shù),SPI和脊髓損傷,微控制器的CAN接口
文件頁數(shù): 118/164頁
文件大小: 1043K
代理商: ST72T2311R7T7
ST72311R, ST72511R, ST72512R, ST72532R
57/164
PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
On overflow, the OVF flag of the CSR register is
set and an overflow interrupt request is generated
if the overflow interrupt enable bit, OIE, in the CSR
register, is set. The OVF flag must be reset by the
user software. This interrupt can be used as a time
base in the application.
External clock and event detector mode
Using the fEXT external prescaler input clock, the
auto-reload timer can be used as an external clock
event detector. In this mode, the ARR register is
used to select the nEVENT number of events to be
counted before setting the OVF flag.
nEVENT = 256 - ARR
When entering HALT mode while fEXT is selected,
all the timer control registers are frozen but the
counter continues to increment. If the OIE bit is
set, the next overflow of the counter will generate
an interrupt which wakes up the MCU.
Figure 34. External Event Detector Example (3 counts)
COUNTER
t
FDh
FEh
FFh
FDh
OVF
CSR READ
INTERRUPT
ARR=FDh
fEXT=fCOUNTER
FEh
FFh
FDh
IF OIE=1
INTERRUPT
IF OIE=1
CSR READ
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