參數(shù)資料
型號(hào): ST72T2311R6T6
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
中文描述: 8位嵌套中斷,EEPROM存儲(chǔ)器,模數(shù)轉(zhuǎn)換器,16位定時(shí)器,8位PWM藝術(shù),SPI和脊髓損傷,微控制器的CAN接口
文件頁數(shù): 10/164頁
文件大小: 1043K
代理商: ST72T2311R6T6
ST72311R, ST72511R, ST72512R, ST72532R
107/164
CONTROLLER AREA NETWORK (Cont’d)
10.7.3.3 Modes of Operation
The CAN Core unit assumes one of the seven
states described below:
– STANDBY. Standby mode is entered either on a
chip reset or on resetting the RUN bit in the Con-
trol/Status Register (CSR). Any on-going trans-
mission or reception operation is not interrupted
and completes normally before the Bit Time Log-
ic and the clock prescaler are turned off for mini-
mum power consumption. This state is signalled
by the RUN bit being read-back as 0.
Once in standby, the only event monitored is the
reception of a dominant bit which causes a wake-
up interrupt if the SCIE bit of the Interrupt Control
Register (ICR) is set.
The STANDBY mode is left by setting the RUN
bit. If the WKPS bit is set in the CSR register,
then the controller passes through WAKE-UP
otherwise it enters RESYNC directly.
It is important to note that the wake-up mecha-
nism is software-driven and therefore carries a
significant time overhead. All messages received
after the wake-up bit and before the controller is
set to run and has completed synchronization
are ignored.
– WAKE-UP. The CAN bus line is forced to domi-
nant for one bit time signalling the wake-up con-
dition to all other bus members.
Figure 57. CAN Controller State Diagram
n
STAN DBY
RESY NC
WAKE-UP
RECEPTI ON
TRANSMIS SION
ERROR
IDLE
ARESET
RUN
RUN & WKPS
RUN & WKP S
FSYN & BOFF & 11 Recessive bits |
(FSYN | BOFF ) & 128 * 11 Recessive bits
RUN
Write to DATA7 |
TX Error & NRTX
Start Of Frame
Arbitration lost
TX Error
RX Error
TX OK
RX OK
BOFF
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