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參數(shù)資料
| 型號(hào)： | ST72P361J4TA |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, PLASTIC, TQFP-44 |
| 文件頁(yè)數(shù)： | 161/224頁(yè) |
| 文件大?。?/td> | 4821K |
| 代理商： | ST72P361J4TA |
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POWER SAVING MODES (Cont’d)
Halt Mode Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
8.5 ACTIVE HALT MODE
ACTIVE HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when MCC/RTC interrupt enable flag
(OIE bit in MCCSR register) is set and when the
AWUEN bit in the AWUCSR register is cleared
The MCU can exit ACTIVE HALT mode on recep-
tion of the RTC interrupt and some specific inter-
rupts (see Table 8, “Interrupt Mapping,” on page
34) or a RESET. When exiting ACTIVE HALT
mode by means of a RESET a 4096 or 256 CPU
cycle delay occurs (depending on the option byte).
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up (see Figure 28).
When entering ACTIVE HALT mode, the I[1:0] bits
in the CC register are are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE
HALT mode is provided by the oscillator interrupt.
Note: As soon as active halt is enabled, executing
a HALT instruction while the Watchdog is active
does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
MCCSR
OIE bit
Power Saving Mode entered when HALT
instruction is executed
0
HALT mode
1
ACTIVE HALT mode
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| ST72T101G2B6 | 功能描述:8位微控制器 -MCU OTP EPROM 8K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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