參數(shù)資料
型號: ST72F324J6
英文描述: 8-BIT MCU WITH NESTED INTERRUPTS. FLASH. 10-BIT ADC. 4 TIMERS. SPI. SCI INTERFACE
中文描述: 8位微控制器嵌套中斷。閃光。 10位ADC。 4定時器。的SPI。 SCI接口
文件頁數(shù): 89/161頁
文件大?。?/td> 2070K
代理商: ST72F324J6
ST72324
33/161
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 19.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
7.4 CONCURRENT & NESTED MANAGEMENT
The following Figure 20 and Figure 21 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 21. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0. The software priority is giv-
en for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Figure 20. Concurrent Interrupt Management
Figure 21. Nested Interrupt Management
MAIN
IT4
IT2
IT1
TRAP
IT1
MAIN
IT0
I1
HA
RD
WA
RE
P
R
IO
RIT
Y
SOFTWARE
3
3/0
3
11
11 / 10
11
RIM
IT
2
IT
1
IT
4
TR
AP
IT
3
IT0
IT3
I0
10
PRIORITY
LEVEL
US
ED
S
TACK
=
1
0
BYT
ES
MAIN
IT2
TRAP
MAIN
IT0
IT2
IT1
IT4
TRA
P
IT3
IT
0
HA
RDWA
R
E
P
R
IO
RIT
Y
3
2
1
3
3/0
3
11
00
01
11
RIM
IT1
IT4
IT1
IT2
IT3
I1
I0
11 / 10
10
SOFTWARE
PRIORITY
LEVEL
USE
D
S
T
ACK
=
2
0
B
YTE
S
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