參數(shù)資料
型號(hào): ST72F324BK2T6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, LQFP-32
文件頁數(shù): 3/167頁
文件大?。?/td> 2651K
代理商: ST72F324BK2T6
On-chip peripherals
ST72323 ST72323L
Bit 1 = SSM SS Management.
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Section : Slave select
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free
for general-purpose I/O)
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of
the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
Data I/O register (SPIDR)
Reset value: undefined
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
Note:
1
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
2
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Caution:
A write to the SPIDR register places data directly into the shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 44).
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
Table 47.
SPI register map and reset values
Address
(hex.)
Register
label
7654321
0
0021h
SPIDR
reset value
MSB
xxxxxxx
LSB
x
0022h
SPICR
reset value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
0023h
SPICSR
reset value
SPIF
0
WCOL
0
OVR
0
MODF
00
SOD
0
SSM
0
SSI
0
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