參數(shù)資料
型號: ST72F321J9
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 5 TIMERS, SPI, SCI, I2C INTERFACE
中文描述: 8位嵌套中斷,閃存,10位ADC,5定時器,SPI和SCI的I2C接口單片機
文件頁數(shù): 119/189頁
文件大?。?/td> 3090K
代理商: ST72F321J9
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ST72321
119/189
I
2
C BUS INTERFACE
(Cont’d)
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register,
holding the
SCL line low
(see
Figure 67
Transfer sequencing
EV8).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
BERR
: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
Note that BERR will not be set if an error is de-
tected during the first or second pulse of each 9-
bit transaction:
Single Master Mode
If a Start or Stop is issued during the first or sec-
ond pulse of a 9-bit transaction, the BERR flag
will not be set and transfer will continue however
the BUSY flag will be reset. To work around this,
slave devices should issue a NACK when they
receive a misplaced Start or Stop. The reception
of a NACK or BUSY by the master in the middle
of communication gives the possibility to reiniti-
ate transmission.
Multimaster Mode
Normally the BERR bit would be set whenever
unauthorized transmission takes place while
transfer is already in progress. However, an is-
sue will arise if an external master generates an
unauthorized Start or Stop while the I
2
C master
is on the first or second pulse of a 9-bit transac-
tion. It is possible to work around this by polling
the BUSY bit during I
2
C master mode transmis-
sion. The resetting of the BUSY bit can then be
handled in a similar manner as the BERR flag
being set.
AF
: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
ARLO:
Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
Note
: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible 0 bits transmitted last. It is then neces-
sary to release both lines by software.
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