參數(shù)資料
型號: ST72E774J9D0
廠商: 意法半導(dǎo)體
元件分類: ADC
英文描述: 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述: 8位USB單片機(jī)的顯示器,高達(dá)60K章檢察官辦公室,每1000內(nèi)存,模數(shù)轉(zhuǎn)換器,定時(shí)器,同步,材質(zhì)單元,脈寬調(diào)制/的BRM,的H / W DDC的
文件頁數(shù): 3/144頁
文件大?。?/td> 1280K
代理商: ST72E774J9D0
ST72774/ST727754/ST72734
100/144
DDC INTERFACE (Cont’d)
The Write and Read operations allow the EDID
data to be downloaded during factory alignment
(for example).
Writes to the memory by the DMA engine can be
inhibited by means of the WP bit in the DCR
register.
A write of the last data structure byte sets a flag
and may be programmed to generate an interrupt
request.
The Data address (sub-address) is either the
second byte of write transfers or is pointed to by
the
internal
address
counter
automatically
incremented after each byte transfer.
Physical address mapping of the data structure
within the memory space is performed with a
dedicated register accessible by software.
4.8.5.1.2 Mode description
DDC1 Mode: This mode is only enabled when the
DDC v2 or P&D-DDC v2 standards are validated. It
transmits only the EDID v1 data (128 bytes).
To switch the DDC1/2B Interface to DDC1 mode,
software must first clear the CF0 bit in the DCR
register while the HWPE bit=0 and then set the
HWPE bit to enable the DDC1/2B Interface.
A proper initialization sequence (see Figure 59)
must supply nine clock pulses on the VSYNCI pin
in order to internally synchronize the device.
During this initialization sequence, the SDA pin is
in high impedance. On the rising edge of the 10th
pulse applied on VSYNCI, the device outputs on
SDA the most significant (MSB) bit of the byte
located at data address 00h.
A byte is clocked out by means of 9 clock pulses
on Vsync, 8 clock pulses for the data byte itself and
an extra pulse for a Don’t Care bit.
As long as SCL is not held low, each byte of the
memory array is transmitted serially on SDA.
The internal address counter is incremented
automatically until the last byte is transmitted.
Then, it rolls over to relative location 00h.
The physical mapping of the data structure
depends on the configuration and on the content of
the AHR register which can be set by software
(see Figure 60).
Figure 59. DDC1 Waveforms
Vsync
SDA
12
8
9
Bit 7
10
11
PE
SCL
Bit 6
ALR
00h
XX
Vsync
SDA
Bit 7
PE
SCL
Bit 6
ALR
00h
7Fh
Bit 7
Bit 6
Bit 0
相關(guān)PDF資料
PDF描述
ST72F324J2 8-BIT MCU WITH NESTED INTERRUPTS. FLASH. 10-BIT ADC. 4 TIMERS. SPI. SCI INTERFACE
ST72F324J4 8-BIT MCU WITH NESTED INTERRUPTS. FLASH. 10-BIT ADC. 4 TIMERS. SPI. SCI INTERFACE
ST72F324J6 8-BIT MCU WITH NESTED INTERRUPTS. FLASH. 10-BIT ADC. 4 TIMERS. SPI. SCI INTERFACE
ST72F324K2 8-BIT MCU WITH NESTED INTERRUPTS. FLASH. 10-BIT ADC. 4 TIMERS. SPI. SCI INTERFACE
ST72F324K4 64Mb EDO/FPM - OBSOLETE
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