參數(shù)資料
型號： ST72C314J4
元件分類： 圖像傳感器
英文描述： CMOS Image Sensor
中文描述： CMOS圖像傳感器
文件頁數(shù)： 86/153頁
文件大?。?/td> 1988K
代理商： ST72C314J4
ST72334J/N, ST72314J/N, ST72124J
38/153
POWER SAVING MODES (Cont’d)
11.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
(MCC/RTC)" on page 52 for more details on the
MCCSR register).
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
mapping,” on page 34) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 25).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 18.1 on page 144 for more details).
Figure 24. HALT Timing Overview
Figure 25. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
HALT
RUN
4096 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
[MCCSR.OIE=0]
HALT INSTRUCTION
RESET
INTERRUPT 3)
Y
N
Y
CPU
OSCILLATOR
PERIPHERALS 2)
I BIT
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
I BIT
ON
OFF
X 4)
ON
CPU
OSCILLATOR
PERIPHERALS
I BITS
ON
X 4)
ON
4096 CPU CLOCK CYCLE
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT 1)
0
WATCHDOG
RESET
1
(MCCSR.OIE=0)
相關PDF資料
PDF描述
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ST72E311N4D0 8-BIT MICROCONTROLLER
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相關代理商/技術參數(shù)
參數(shù)描述
ST72C314J4B1 制造商:STMicroelectronics 功能描述:ST72FLASH 8K - Bulk
ST72C314J4B6 功能描述:8位微控制器 -MCU Flash 16K SPI/SCI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
ST72C314J4T1 制造商:STMicroelectronics 功能描述:ST72FLASH 8K - Bulk
ST72C314J4T6 功能描述:8位微控制器 -MCU Flash 16K SPI/SCI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
ST72C314J4T6 PROGRAMMED 制造商:STMicroelectronics 功能描述:MCU 8-bit ST7 CISC 16KB Flash 3.3V/5V 44-Pin TQFP Tray
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