參數(shù)資料
型號： ST72C254G2M7
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY. ADC. 16-BIT TIMERS. SPI.
中文描述： 8位單電壓閃存微控制器。 ADC的。 16位定時器。的SPI。
文件頁數(shù)： 26/140頁
文件大?。?/td> 1349K
代理商： ST72C254G2M7
ST72104G, ST72215G, ST72216G, ST72254G
121/140
14.9 CONTROL PIN CHARACTERISTICS
14.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Figure 86. Typical Application with RESET pin 8)
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The IIO current sunk must always respect the absolute maximum rating specified in Section 14.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-
scribed in Figure 87). This data is based on characterization results, not tested in production.
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
VIL
Input low level voltage 2)
0.3xVDD
V
VIH
Input high level voltage 2)
0.7xVDD
Vhys
Schmitt trigger voltage hysteresis 3)
400
mV
VOL
Output low level voltage 4)
(see Figure 88, Figure 89)
VDD=5V
IIO=+5mA
0.68
0.95
V
IIO=+2mA
0.28
0.45
RON
Weak pull-up equivalent resistor 5)
VIN=VSS
VDD=5V
20
40
60
k
VDD=3.4V
80
100
120
tw(RSTL)out Generated reset pulse duration
External pin or
internal reset sources
6
30
1/fSFOSC
s
th(RSTL)in External reset pulse hold time
6)
20
s
tg(RSTL)in Filtered glitch duration
7)
100
ns
RESET
VDD
WATCHDOG RESET
ST72XXX
LVD RESET
INTERNAL
RON
0.1
F
VDD
0.1
F
VDD
4.7k
EXTERNAL
RESET
CIRCUIT 8)
RESET CONTROL
OP
TI
ON
A
L
USER
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