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參數(shù)資料
| 型號(hào)： | ST72651R6T1 |
| 英文描述： | ST7 - LOW-POWER. FULL-SPEED USB 8-BIT MCU WITH 32K FLASH. 5K RAM. FLASH CARD I/F. TIMER. PWM. ADC. I2C |
| 中文描述： | ST7的-低功耗。全速USB 8位32K快閃微控制器。 5K內(nèi)存。閃存卡的I /樓計(jì)時(shí)器。脈寬調(diào)制。 ADC的。的I2C |
| 文件頁(yè)數(shù)： | 109/166頁(yè) |
| 文件大?。?/td> | 2089K |
| 代理商： | ST72651R6T1 |
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ST7265x
47/166
8 POWER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (fCPU).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
The user can also switch off any unused on-chip
peripherals
individually
by
programming
the
MISCR2 register.
8.2 WAIT MODE
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I1:0] bits in the CC register are forced to 0, to
enable all interrupts. All other registers and mem-
ory remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup-
on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 33.
Figure 33. WAIT Mode Flow Chart
WFI INSTRUCTION
RESET
INTERRUPT
Y
N
Y
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I1:0] BITS
ON
CLEARED
OFF
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I1:0] BITS
ON
SET
ON
FETCH RESET VECTOR
OR SERVICE INTERRUPT
DELAY
IF RESET
Note: Before servicing an interrupt, the CC
register is pushed on the stack. The I1:0] bits are
set during the interrupt routine and cleared
when the CC register is popped.
(Refer to Figure 20 and
1
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