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參數(shù)資料
| 型號： | ST72361AR6TA |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 102/224頁 |
| 文件大?。?/td> | 4821K |
| 代理商： | ST72361AR6TA |
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12.8 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
12.8.1
Functional
EMS
(Electro
Magnetic
Susceptibility)
Based on a simple running application on the
product (toggling two LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD and VSS through
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
12.8.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behavior
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
12.8.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling two LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Notes:
1. Not tested in production.
Symbol
Parameter
Conditions
Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
VDD = 5V, TA = +25°C, fOSC = 8 MHz
conforms to IEC 1000-4-2
3B
VFFTB
Fast transient voltage burst limits to be applied
through 100pF on VDD and VDD pins to induce a func-
tional disturbance
VDD = 5V, TA = +25°C, fOSC = 8 MHz
conforms to IEC 1000-4-4
Symbol
Parameter
Conditions
Monitored
Frequency Band
Max vs. [fOSC/fCPU]
Unit
8/4 MHz
16/8 MHz
SEMI
Peak level
Flash devices: VDD = 5V, TA = +25°C,
LQFP64 package
conforming to SAE J 1752/3
0.1 MHz to 30 MHz
31
32
dBV
30 MHz to 130 MHz
32
37
130 MHz to 1 GHz
11
16
SAE EMI Level
3.0
3.5
-
ROM devices: VDD = 5V, TA = +25°C,
LQFP64 package
conforming to SAE J 1752/3
0.1 MHz to 30 MHz
10
18
dBV
30 MHz to 130 MHz
15
25
130 MHz to 1 GHz
-3
1
SAE EMI Level
2.0
2.5
-
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