參數(shù)資料
型號(hào): ST72344K4T6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, ROHS COMPLIANT, TQFP-32
文件頁(yè)數(shù): 243/246頁(yè)
文件大?。?/td> 2016K
代理商: ST72344K4T6
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On-chip peripherals
ST72344xx, ST72345xx
Figure 43.
16-bit read sequence (from either the counter register or the alternate
counter register)
The user must read the MS Byte first, then the LS Byte value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS Byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, one-pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
The TOF bit of the SR register is set.
A timer interrupt is generated if:
TOIE bit of the CR1 register is set and
I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1.
Reading the SR register while the TOF bit is set.
2.
An access (read or write) to the CLR register.
Note:
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (Device awakened by an interrupt) or from the reset count (Device
awakened by a Reset).
External clock
The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronised with the falling edge of the internal CPU clock.
is buffered
Read
At t0
Read
Returns the buffered
LS Byte value at t0
At t0 +
Δt
Other
instructions
Beginning of the sequence
Sequence completed
LS Byte
MS Byte
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