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參數(shù)資料
| 型號： | ST72324BLK4B5 |
| 廠商： | 意法半導體 |
| 英文描述： | 3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE |
| 中文描述： | 3V左右8位8到32K閃存/ ROM，10位ADC，4個定時器，SPI和SCI接口控制器 |
| 文件頁數(shù)： | 67/151頁 |
| 文件大?。?/td> | 1209K |
| 代理商： | ST72324BLK4B5 |
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ST72F324L, ST72324BL
67/151
16-BIT TIMER
(Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 =
OC1E
Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 =
OC2E
Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note:
In Flash devices, this bit is not available for
Timer A. It must be kept at its reset value.
Bit 5 =
OPM
One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 =
PWM
Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Bit 3, 2 =
CC[1:0]
Clock Control.
The timer clock mode depends on these bits:
Table 16. Clock Control Bits
Note
: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 =
IEDG2
Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 =
EXEDG
External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Timer Clock
f
CPU
/ 4
f
CPU
/ 2
f
CPU
/ 8
External Clock (where
available)
CC1
0
0
1
CC0
0
1
0
1
1
1
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相關代理商/技術參數(shù) |
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| ST72324BLK4B6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
| ST72324BLK4BA | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE |
| ST72324BLK4T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
| ST72324BLK4T5 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
| ST72324BLK4T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
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