參數(shù)資料
型號： ST72324BLJ2TA/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, TQFP-44
文件頁數(shù)： 144/151頁
文件大?。?/td> 1209K
代理商： ST72324BLJ2TA/XXX
ST72F324L, ST72324BL
92/151
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.9 Clock Deviation Causes
The causes which contribute to the total deviation
are:
–DTRA: Deviation due to transmitter error (Local
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
–DQUANT: Error due to the baud rate quantisa-
tion of the receiver.
–DREC: Deviation of the local oscillator of the
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
–DTCL: Deviation due to the transmission line
(generally due to the transceivers)
All the deviations of the system should be added
and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75%
10.5.4.10 Noise Error Causes
See also description of Noise error in Section
Start bit
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling
edge is considered to be valid if the 3 consecu-
tive samples before the falling edge occurs are
detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
2. During sampling of the 16 samples, if one of the
samples numbered 8, 9 or 10 is detected as a
“1”.
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
Figure 52. Bit Sampling in Reception Mode
RDI LINE
Sample
clock
12345678910
11
12
13
14
15
16
sampled values
One bit time
6/16
7/16
1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST72324BLJ4 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
ST72324BLJ4B1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface
ST72324BLJ4B5 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface
ST72324BLJ4B6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface
ST72324BLJ4BA 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
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