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參數(shù)資料
| 型號： | ST70135A |
| 廠商： | 意法半導體 |
| 英文描述： | ASCOTTM DMT TRANSCEIVER |
| 中文描述： | ASCOTTM大唐收發(fā)器 |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 198K |
| 代理商： | ST70135A |
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ST70135A
14/29
DMT Symbol Timing Unit (DSTU)
The DSTU interfaces with various modules, like
DSP FrontEnd, FFT/IFFT,Mapper/Demapper RS,
Monitor and Transceiver Controller. It consists of a
real time and a scheduler modules. The real time
unit generates a timebase for the DMT symbols
(sample counter), superframes (symbol counter)
and hyper-frames (sync counter). The timebases
can be modified by various control features. They
are continuously fine-tuned by the DPLL module.
The
DSTU
schedulers
controlled by program opcodes and a set of
variables, the most important of which are real
time
counters.
The
sequencers are completely independent and run
different
programs.
An
variables is assigned to each of them. The
sequencer programs can be updated in real time.
execute a
program,
transmit
and
receive
independent
set
of
ST70135A interfaces
Overview
See Figure 9.
Processor Interface (ATC)
The ST70135A is controlled and configured by an
external processor across the processor interface.
All programmable coefficients and parameters are
loaded through this path.
Data and addresses are multiplexed
ST70135A works in 16 bits data access, so
address bit 0 is not used. Address bit 1 is not
multiplexed with data. It has its own pin : BE1.
Byte access are not supported. Access cycle read
or write are always in 16 bits data wide, ie bit
address A0 is always zero value.
The interruptrequest pin to the processor is INTB,
and is an Open Drain output.
The ST70135A supports both little and big endian.
The default feature is big endian.
Figure 9 :
ST70135A Interfaces
Generic Interface
This interface is suitable for a number of
processors using a multiplexedAddress/data bus.
In this case, synchronization of the input signals
with PCLK pin is not necessary.
AFEINTERFACETOADSLLINE(ST70134)
RESET
JTAG
CLOCK
PROCESSOR
INTERFACE
(ATC)
DIGITALINTERFACEUTOPIA/BITSTREAM INTERFACE
ST70135A
Figure 10 :
Generic Processor Interface Write Timing Cycle
T
alew
Twr2cs
T
avs
T
avh
T
ale2cs
T
wr2d
T
wdvd
T
dvh
T
cs2rdy
T
cs2wr
T
wrw
T
mclk
T
csre
T
rdy2wr
ALE
CSB
AD(15-0)
WRB
READY
RDB
相關(guān)PDF資料 |
PDF描述 |
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| ST70136 | CPE ADSL ANALOG FRONT END |
| ST70136B | CPE ADSL ANALOG FRONT END |
| ST70136G | CPE ADSL ANALOG FRONT END |
| ST70137 | UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST70136 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136Q | 功能描述:射頻無線雜項 ADSL Analg Front-End RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel |
| ST70137 | 制造商:STMicroelectronics 功能描述: |
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