
45/84
ST6365, ST6375, ST6385 ST6367, ST6377, ST6387
4.6 AFC A/D COMPARATOR
The AFC macrocell contains an A/D comparator
with five levels at intervals of 1V from 1V to 5V.
The levels can all be lowered by 0.5V to effectively
double the resolution.
4.6.1 A/D Comparator
The A/D used to perform the AFC function (when
high threshold is selected) has the following volt-
age levels: 1,2,3,4 and 5V. Bits 0-2 of AFC result
register (E4h address) will provide the result in bi-
nary form (less than 1V is 000, greater than 5V is
101).
If the application requires a greater resolution, the
sensitivity can be doubled by clearing to zero bit 2
of the OUTPUTS control register, address E5h. In
this case all levels are shifted lower by 0.5V. If the
two results are now added within a software rou-
tine then the A/D S-curve can be located within a
resolution of 0.5V.
The A/D input has high impedance able to with-
stand up to 13V signals (input level tolerances
± 200mV absolute and ± 100mV relative to 5V).
Figure 30. AFC Input Configuration
AFC, IR and OSD Result Register (AFCR)
Address: E4h - Read only
Reset Value: 00h
D7-D5. These bits are not used.
VSYNC. This bit reads the status of the VSYNC
pin. It is inverted with respect to the pin.
IR. This bit reads the status of the IR latch. If a sig-
nal has been latched this bit will be high.
AD2-AD0. These bits store the real time conver-
sion of the value present on the AFC input pin. Un-
defined reset value.
AFC Shift Register (AFSR)
Address: E4h - Write only
Reset Value: 00h
D7, D6, D5, D4, D3, D1, D0. These bits are not
used.
ADCR3. This bit determines the voltage range of
the AFC input. Writing a zero will select the 0.5V to
4.5V range. Writing a one will select the 1.0V to
5.0V range. Undefined after reset.
Caution: This register contains at least one write
only bit. Single bit instructions (SET, RES, INC
and DEC) should not be used.
VA00458
AFC
A
In
AFC (INPUT, HIGH IMPEDANCE)
70
-
VSYNC
IR
AD2
AD1
AD0
70
--
-
ADSR3
--