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參數(shù)資料
| 型號： | ST6263BB1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 8位檢察官辦公室/存儲器與阿微控制器/ D轉(zhuǎn)換器，自動重加載定時器，EEPROM和的SPI |
| 文件頁數(shù)： | 51/75頁 |
| 文件大?。?/td> | 540K |
| 代理商： | ST6263BB1 |
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ST62T53B/T60B/T63B ST62E60B
SERIAL PERIPHERAL INTERFACE SPI
(Cont’d)
SPI DIV Register (DIV)
Address: E1h
—
Read/Write
Reset status: 00h
The SPIDIV register defines the transmission rate
and frame format and contains the interrupt flag.
Bits CD0-CD2, DIV3-DIV6 are read/write while
SPINT can be read and cleared only. Write access
is not allowed if SPRUN in the MOD register isset.
Bit 7 =
SPINT
: Interrupt Flag.Itis automatically set
to one by the SPI at the end of a transmission or
reception and an interrupt request can be generat-
ed depending on the state of the interrupt mask bit
in the MOD control register. This bit is read-only
and must be cleared by user software at the end of
the interrupt service routine.
Bit 6-3 =
DIV6-DIV3
: Burst Mode Bit Clock Period
Selection.Definethenumberofshiftregisterbitsthat
aretransmittedorreceived inaframe.Theavailable
selections are listed inFigure 18. The normal max-
imumsettingis8bits,sincetheshift register is8bits
wide. Note that by setting a greater number of bits,
inconjunction with theSPIN bitintheMODregister,
unwanted data bits may be filtered from the data
stream.
Bit 2-0 =
CD2-CD0
: Base/Bit Clock Rate Selec-
tion Define the division ratio between the core
clock (f
INT
divided by 13) and the clock supplied to
the Shift Register in Master mode.
Table 17.Base/Bit Clock Ratio Selection
Note
: For example, when an 8MHz CPU clock is
used, asynchronous operation at 9600 Baud is
possible (8MHz/13/64). Other Baud rates are
available by proportionally selecting division fac-
tors depending on CPU clock frequency.
Data setup timeon Sin istypically 250ns min, while
data hold time is typically 50ns min.
Table 18.Burst Mode Bit Clock Periods
SPI Data/Shift Register (SPIDSR)
Address: E0h
—
Reset status: XXh
Read/Write
SPIDSR is read/write, however write access is not
allowed if the SPRUN bit of Mode Control register
is set to one.
Data is sampled into SPDSR on theSCK edge de-
termined by the CPOL and CPHA bits. The affect
of these setting is shown in the following diagrams.
The Shift Register transmits and receives the Most
Significant Bit first.
Bit 7-0 =
DSR7-DSR0
: Data Bits. These are the
SPI shift register data bits.
Miscellaneous Register (MISCR)
Address: DDh
—
Write only
Reset status: xxxxxxxb
Bit 7-1 =
D7-D1
: Reserved.
Bit 0 =
D0
: Bit 0. This bit, when set, selects the
Sout pin as the SPI output line. When this bit is
cleared, Sout acts as a standard I/O line.
7
0
SPINT
DOV6
DIV5
DIV4
DIV3
CD2
CD1
CD0
CD2-CD0
0
0
1
1
0
0
1
1
Divide Ratio (decimal)
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 256
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
DIV6-DIV3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Number of bits sent
Reserved (not to be used)
1
2
3
4
5
6
7
8
9
10
11
Refer to the
12
description of the
13
DIV6-DIV3 bits in
14
the DIV Register
15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
-
-
-
-
-
-
-
D0
51
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST6263BB3 | 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI |
| ST6253BM6 | Replaced by PT78HT253 : 5.25Vout 2A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85 |
| ST6253CB3 | Replaced by PT78HT253 : 5.25Vout 2A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85 |
| ST6253CB6 | Replaced by PT78HT253 : 5.25Vout 2A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85 |
| ST6253CM1 | Replaced by PT78HT265 : 6.5Vout 2A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST6263BB1/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI |
| ST6263BB3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI |
| ST6263BB3/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI |
| ST6263BB6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI |
| ST6263BB6/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI |
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