參數(shù)資料
型號: ST6240BQ6/XXX
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, QFP-80
文件頁數(shù): 30/73頁
文件大?。?/td> 1963K
代理商: ST6240BQ6/XXX
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
36/73
ST62T40B/E40B
I/O PORTS (Cont’d)
4.1.3 LCD alternate functions (combiports)
PC0 to PC7 can also be individually defined as 8
LCD segment output by setting DDRC, ORC and
DRC registers as shown in Table 15.
On the contrary with other I/O lines, the reset state
is the LCD output mode. These 8 segment lines are
recognised as S33..S40 by the embedded LCD
controller drive.
4.1.4 SPI alternate functions
PB6/Sin and PB5/Scl pins must be configured as
input through the DDR and OR registers to be
used data in and data clock (Slave mode) for the
SPI. All input modes are available and I/O's can be
read independantly of the SPI at any time.
PB7/Sout must be configured in open drain output
mode to be used as data out for the SPI. In output
mode, the value present on the pin is the port data
register content only if PB7 is defined as push pull
output, while serial transmission is possible only in
open drain mode.
Table 15. PC0-PC7 Combiport Option Selection
Note: X = Don’t care
Figure 20. Peripheral Interface Configuration of SPI
DDR
OR
DR
Mode
Option
0
Input
With pull-up, no interrupt
0
1
Input
No pull-up, no interrupt
0
1
0
Input
With pull-up and with interrupt
0
1
Input
LCD segment (Reset state)
1
0
X
Output
Open-drain output
1
X
Output
Push-pull output
PB7/Sout
PB6/Sin
PB5/Scl
PID
OPR
DR
1
MUX
0
OUT
IN
SYNCHRONOUS
SERIAL I/O
CLOCK
PID
DR
PID
DR
PP/OD
VR01661F
36
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